Micro-architecture estimation of the useless power consumption of a high-performance processor

The purpose of this work is to evaluate the useless power consumption of a micro-processor that is, the power dissipated to perform those tasks that are not useful for the ultimate goal of committing instructions. This is a first-order estimation of the useless power consumption. A generic high-performance processor is divided in its basic micro-architecture blocks and the amount of useful and useless accesses to each of these blocks is estimated through simulations. The useless power consumption is further divided into useless power when: (a) executing instructions within a mispredicted path, and (b) then executing instructions that will be eventually committed by some of the block accesses performed by these instructions are not needed. The simulations performed indicate that if the useless power dissipation of a high-performance processor could be totally removed (at the cost of no IPC degradation), the overall processor power consumption would be reduced by as much as 65% compared to the same processor in which all the blocks are accessed every cycle.