An 0.25 /spl mu/m CMOS injection locked 5.6 Gb/s clock and data recovery cell

Abstract

The harmonic clock signals in a 5.6 Gb/s NRZ (Non Return to Zero) 2/sup 7/-1 pseudo-random data stream are used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is deserialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock. This architecture offers power savings since the data and clock rate are reduced immediately by a factor of two. A measured Bit Error Rate (BER) of less than 2E-13 at 5.6 Gb/s is achieved using a conventional 0.25 /spl mu/m CMOS technology.