Logic and high level synthesis for communication protocols

This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols through logic and high level synthesis (HLS). The implementation results of different description styles of protocols and a comparison of the protocol implementation using the HLS technique with a standard cells library and the implementation using a Programmable Logic Device (PLD) are presented. The results include area analysis and clock frequency evaluation of the synthesized hardware.