架构师用于可重构计算的工作台

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI:10.1109/SBCCI.1999.803110

R. Skliarova, A. Ferrari

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引用次数: 1

摘要

本文描述了一个32位处理器核心的FPGA实现，以及一套开发的工具来支持可重构计算处理器核心的设计。基本架构是MIPS16 ISA的一个子集，它是针对嵌入式系统的MIPS架构的16位版本。这些工具构成了一个计算机架构工作台，允许通过微程序的规范来定义新的指令，以实现它们，模拟逐步执行的指令，并显示生成的控制信号和数据路径中相应的数据流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An architect's workbench for reconfigurable computing

This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.

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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)

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