Register files constraint satisfaction during scheduling of DSP code

Abstract

Algorithms in digital signal processing (DSP) impose tight timing constraints that the compiler has to respect while considering the limited capacity of the available register files in a target DSP processor. Traditional code generation methods that schedule spill code to satisfy storage capacity may take many iterations and are usually not capable of satisfying the timing constraints. In this paper we present a new method to handle register file capacity constraints during scheduling. The method identifies potential bottlenecks for register binding and subsequently serializes the lifetimes of values until it can be guaranteed that all capacity constraints will be satisfied after scheduling. Experiments show that we efficiently obtain high quality instruction schedules for DSP kernels.