An architect's workbench for reconfigurable computing

Abstract

This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.