A 9-bit parallel pipelined multiplier based on the 3-bit recoding from Booth's algorithm

Abstract

This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.