基于布斯算法的3位重编码的9位并行流水线乘法器

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI:10.1109/SBCCI.1999.802974

L. Caldeira, T. Pimenta, E. Cotrim

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引用次数: 0

摘要

本文提出了一种基于Booth算法的9位并行乘法器的设计，采用3位重编码。虽然在文献中提到“可能”，但没有关于其实现的参考文献。与仅使用2位的传统实现相比，该乘法器提供了更高的乘法速度，并提供了良好的速度/面积比。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 9-bit parallel pipelined multiplier based on the 3-bit recoding from Booth's algorithm

This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.

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Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)

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