用于数字抽取的高速FIR滤波器

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387) Pub Date : 1999-09-29 DOI:10.1109/SBCCI.1999.803103

M. Brambilla, D. Guidi, V. Liberali

{"title":"用于数字抽取的高速FIR滤波器","authors":"M. Brambilla, D. Guidi, V. Liberali","doi":"10.1109/SBCCI.1999.803103","DOIUrl":null,"url":null,"abstract":"This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in /spl Sigma//spl Delta/ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"82 11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"High speed FIR filters for digital decimation\",\"authors\":\"M. Brambilla, D. Guidi, V. Liberali\",\"doi\":\"10.1109/SBCCI.1999.803103\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in /spl Sigma//spl Delta/ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.\",\"PeriodicalId\":342390,\"journal\":{\"name\":\"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)\",\"volume\":\"82 11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-09-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBCCI.1999.803103\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.1999.803103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

本文介绍了一种采用无乘法器结构实现的多级FIR抽取滤波器。该滤波器设计用于亚微米CMOS技术的/spl Sigma//spl Delta/ A/D转换器。该架构旨在提高运算速度，同时限制功耗，从而减少开关噪声注入基片和数字/模拟串扰。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

High speed FIR filters for digital decimation

This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in /spl Sigma//spl Delta/ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)

自引率

0.00%

发文量