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2017 Symposium on VLSI Technology最新文献

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10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling 共同开发的10nm高性能移动SoC设计和技术，可实现性能，功耗和面积缩放
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998203
Sam Yang, Yanxiang Liu, M. Cai, Jerry Bao, P. Feng, Xiangdong Chen, L. Ge, Jun Yuan, Jihong Choi, Ping Liu, Youseok Suh, Hao Wang, Jie Deng, Yandong Gao, Jackie Yang, Xiao-Yong Wang, Dang-qiang Yang, John Zhu, P. Pénzes, S. C. Song, Chulyong Park, Sungwon Kim, Jedon D. Kim, S. Kang, E. Terzioglu, K. Rim, P. Chidambaram
{"title":"10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling","authors":"Sam Yang, Yanxiang Liu, M. Cai, Jerry Bao, P. Feng, Xiangdong Chen, L. Ge, Jun Yuan, Jihong Choi, Ping Liu, Youseok Suh, Hao Wang, Jie Deng, Yandong Gao, Jackie Yang, Xiao-Yong Wang, Dang-qiang Yang, John Zhu, P. Pénzes, S. C. Song, Chulyong Park, Sungwon Kim, Jedon D. Kim, S. Kang, E. Terzioglu, K. Rim, P. Chidambaram","doi":"10.23919/VLSIT.2017.7998203","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998203","url":null,"abstract":"The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130829094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A shutter-less micro-bolometer thermal imaging system using multiple digital correlated double sampling for mobile applications 一种无快门微辐射热计热成像系统，使用多个数字相关双采样用于移动应用
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998141
Seunghyun Park, Tei Cho, Minsik Kim, Hyungchul Park, Kwyro Lee
{"title":"A shutter-less micro-bolometer thermal imaging system using multiple digital correlated double sampling for mobile applications","authors":"Seunghyun Park, Tei Cho, Minsik Kim, Hyungchul Park, Kwyro Lee","doi":"10.23919/VLSIT.2017.7998141","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998141","url":null,"abstract":"A micro-bolometer focal plane array (MBFPA)-based long wavelength Infra-red thermal imaging sensor is presented. The proposed multiple digital correlated double sampling (MD-CDS) readout method employing newly designed reference-cell greatly reduces PVT variation-induced fixed pattern noise (FPN) and as a result features much relaxed calibration process, easier TEC-less operation and Shutter-less operation. The readout IC and MBFPA was fabricated in 0.35um CMOS and amorphous silicon MEMS process respectively. The fabricated MBFPA thermal imaging sensor has NETD performance of 0.1 kelvin even though the mechanical shutter is not used.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130971380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10MHz 5-to-40V EMI-regulated GaN power driver with closed-loop adaptive Miller Plateau sensing 具有闭环自适应米勒高原传感的10MHz 5- 40v emi稳压GaN功率驱动器
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008573
Yingping Chen, Xugang Ke, D. Ma
{"title":"A 10MHz 5-to-40V EMI-regulated GaN power driver with closed-loop adaptive Miller Plateau sensing","authors":"Yingping Chen, Xugang Ke, D. Ma","doi":"10.23919/VLSIC.2017.8008573","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008573","url":null,"abstract":"To optimize the classic design trade-off between EMI noise and power efficiency in GaN power drivers at 10MHz and beyond, a closed-loop adaptive Miller Plateau sensing (AMPS) technique is proposed. In order to mitigate long delays and low accuracy issues in conventional Miller Plateau (MP) sensing approaches, an emulated MP tracking (EMPT) technique is adopted to achieve instant MP start point sensing. An isolated negative voltage sensor is designed for the EMPT to avoid considerable leakage current and enhance reliability without increasing circuit complexity. A noise-isolated feedback link ensures the closed-loop regulation accuracy by blocking the switching noise between HV and LV operation domains. Fabricated in a 0.35μm BCD process, the design achieves EMI reduction of 19.23dBμV in Band B (<30MHz) and over 9dBμV in Band C/D (>30MHz).","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"2 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133042290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Impact of strain on access resistance in planar and nanowire CMOS devices 应变对平面和纳米线CMOS器件存取电阻的影响
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998180
R. Berthelon, F. Andneu, F. Triozon, M. Cassé, L. Bourdet, G. Ghibaudo, D. Rideau, Y. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet
{"title":"Impact of strain on access resistance in planar and nanowire CMOS devices","authors":"R. Berthelon, F. Andneu, F. Triozon, M. Cassé, L. Bourdet, G. Ghibaudo, D. Rideau, Y. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet","doi":"10.23919/VLSIT.2017.7998180","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998180","url":null,"abstract":"We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R<inf>ACC</inf>) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R<inf>acc</inf> (−21% for 4 V V<inf>b</inf> and −53% for −1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε<inf>n/p</inf>=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"395 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123960844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation challenges for scalable neuromorphic computing 可扩展神经形态计算的实现挑战
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008582
S. Yamamichi, A. Horibe, T. Aoki, K. Hosokawa, T. Hisada, H. Mori
{"title":"Implementation challenges for scalable neuromorphic computing","authors":"S. Yamamichi, A. Horibe, T. Aoki, K. Hosokawa, T. Hisada, H. Mori","doi":"10.23919/VLSIC.2017.8008582","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008582","url":null,"abstract":"In the big data era, a new computing system, called Cognitive Computing, that can handle unstructured data, learn and extract the insights is required. A neuromorphic device is a key component for this, and several architectures are reported. Compared to the neuromorphic device with SRAM-based spiking neural network, a cross-bar structure device realizes on-chip leaning, but requires high-density off-chip interconnect, much higher than those for conventional high-end logic devices. Recent progress of solder bumping and 3-dimentional integration technologies are described.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power Cu atom switch programmable logic fabricated in a 40nm-node CMOS technology 采用40nm节点CMOS技术制备的低功耗Cu原子开关可编程逻辑
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998188
X. Bai, T. Sakamoto, M. Tada, M. Miyamura, Y. Tsuji, A. Morioka, R. Nebashi, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi
{"title":"A low-power Cu atom switch programmable logic fabricated in a 40nm-node CMOS technology","authors":"X. Bai, T. Sakamoto, M. Tada, M. Miyamura, Y. Tsuji, A. Morioka, R. Nebashi, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi","doi":"10.23919/VLSIT.2017.7998188","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998188","url":null,"abstract":"For the first time, a 40nm-node, 2x logic density, 3.8x operation speed, and 3x power efficient, nonvolatile programmable logic (NPL) is demonstrated by using Cu atom switch for configuration switches. The switching characteristics of the atom switch are kept in scaling down to 64/32nm device area, and an improved PSE reduces set voltage while keeping low leakage current, enabling core transistors to select the atom switches. The developed 40nm NPL is a strong candidate for the next wave of energy-efficient computing.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125546941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Computing platform for automotive electronics of automated driving generation 自动驾驶一代汽车电子计算平台
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008578
Hideki Sugimoto
{"title":"Computing platform for automotive electronics of automated driving generation","authors":"Hideki Sugimoto","doi":"10.23919/VLSIC.2017.8008578","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008578","url":null,"abstract":"This paper addresses requirements from future automotive electronics system concept/design to computing technology or platform filling processing characteristics which will be used in applications of automated driving generation. We cannot completely predict future trends of functionality or application, so it is important to have flexible and scalable computing platform for that generation. The platform should also have a reasonable coverage of processing characteristics especially for parallelism point of view, because it will strongly affect to automotive electronics system efficiency and quality. Here, we'll mainly point to automotive unique processing characteristics which should be improved in near future.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μA/μm at Ioff = 100 nA/μm and VD = 0.5 V 垂直异质结InAs/InGaAs纳米线mosfet在Si上，离子= 330 μA/μm, Ioff = 100 nA/μm, VD = 0.5 V
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998191
Olli-Pekka Kilpi, Jun Wu, J. Svensson, E. Lind, L. Wernersson
{"title":"Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μA/μm at Ioff = 100 nA/μm and VD = 0.5 V","authors":"Olli-Pekka Kilpi, Jun Wu, J. Svensson, E. Lind, L. Wernersson","doi":"10.23919/VLSIT.2017.7998191","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998191","url":null,"abstract":"We present vertical InAs nanowire MOSFETs on Si with an In<inf>0.7</inf>Ga<inf>0.3</inf>As drain. The devices show Ion and gm/SS record performance for vertical MOSFETs and I<inf>off</inf> below 1 nA/μm at V<inf>d</inf> 0.5 V. We show a device with gm=1.4 mS/μm and SS=85 mV/dec, therefore having Q-value (gm/SS) of 16. The device has I<inf>on</inf>=330 μA/μm and 46 μA/μm at Ioff 100 nA/μm and 1 nA/μm, respectively. Furthermore, we show a device with SS=68 mV/dec and I<inf>on</inf>=88 μA/μm at I<inf>off</inf> 1 nA/μm and V<inf>d</inf> 0.5 V.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116887596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Distributed quantum computing systems: Technology to quantum circuits 分布式量子计算系统:量子电路技术
2017 Symposium on VLSI Technology Pub Date : 1900-01-01 DOI: 10.23919/vlsit.2017.7998147
R. Van Meter
{"title":"Distributed quantum computing systems: Technology to quantum circuits","authors":"R. Van Meter","doi":"10.23919/vlsit.2017.7998147","DOIUrl":"https://doi.org/10.23919/vlsit.2017.7998147","url":null,"abstract":"Quantum computers, both solid-state and other, are developing rapidly in the laboratory and commercialization has begun. We discuss their potential applications and the challenges of manufacturing, managing errors, and creating full-scale systems.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique 利用反采样链(BSC)技术统计表征14nm三栅极CMOS的辐射诱发脉冲波形和触发器软误差
2017 Symposium on VLSI Technology Pub Date : 1900-01-01 DOI: 10.23919/vlsit.2017.7998134
Saurabh Kumar, M. Cho, L. Everson, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, H. Quinn, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim
{"title":"Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique","authors":"Saurabh Kumar, M. Cho, L. Everson, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, H. Quinn, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim","doi":"10.23919/vlsit.2017.7998134","DOIUrl":"https://doi.org/10.23919/vlsit.2017.7998134","url":null,"abstract":"A novel BSC circuit with tunable current starved buffers demonstrates higher sensitivity, scalability & accurate statistical characterization of radiation-induced SET pulse waveforms & flip-flop SER in 14nm tri-gate CMOS, thus enabling improved SER estimation & analysis for a range of supply voltages including NTV.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129458966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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