2017 Symposium on VLSI Technology最新文献

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Towards a fully integrated, wirelessly powered, and ordinarily equipped on-lens system for successive dry eye syndrome diagnosis 迈向一个完全集成的、无线供电的、通常配备的、用于干眼综合征连续诊断的晶状体系统
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998210
J. Chiou, S. Hsu, Yu-Chieh Huang, Guan-Ting Yeh, Kai-Shiun Dai, Cheng-Kai Kuei
{"title":"Towards a fully integrated, wirelessly powered, and ordinarily equipped on-lens system for successive dry eye syndrome diagnosis","authors":"J. Chiou, S. Hsu, Yu-Chieh Huang, Guan-Ting Yeh, Kai-Shiun Dai, Cheng-Kai Kuei","doi":"10.23919/VLSIT.2017.7998210","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998210","url":null,"abstract":"This paper presents a smart contact lens (SCL) sensor system for successive evaluation of tear evaporation. The proposed SCL system integrated with 3D technology is composed of tunable sensitivity sensor-readout circuitry, a tear sensor, and an antenna, and is embedded into a biocompatible hydrogel-based contact lens by a commercial manufacturing process. Moreover, the on-lens system can be addressed using commercial radio-frequency identification (RFID) reader devices for sensor control and data communication. Subjects can wear the SCL for continuous tear-content monitoring. Furthermore, the recordings from the device can provide high distinguishability in different tear phantoms using a variation of capacitance or resistance rather than using the weight loss.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On-die 16nm metal critical peak current test methodology with 100ps pulse width 片上16nm金属临界峰值电流测试方法,100ps脉冲宽度
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998150
Yu-Tao Yang, W. Chou, Ming-Hsien Lin, P.-Z. Kang, A. Oates, Y. Peng
{"title":"On-die 16nm metal critical peak current test methodology with 100ps pulse width","authors":"Yu-Tao Yang, W. Chou, Ming-Hsien Lin, P.-Z. Kang, A. Oates, Y. Peng","doi":"10.23919/VLSIT.2017.7998150","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998150","url":null,"abstract":"A new methodology to measure the product-like AC stress of metal critical peak current was implemented in 16nm High-K Metal Gate (HKMG) FINFET process. Traditional TLP tester can only generate minimum 1ns pulse width stress, which is still in thermal diffusion metal burn out regime. The proposed method can generate minimum pulse width of 100ps stress waveform through on-die tunable pulse-width generator and time-to-current duty detector circuits. The silicon data first demonstrated Cu critical peak current will enter the adiabatic regime under 100ps pulse width with 10X peak current than in thermal diffusion regime. This wafer-level measurable test vehicle can be put on scribe-line as Design-For-Manufacturing (DFM) DC-to-AC metal reliability monitor system.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114553969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
One and two dimensional nanocarbon materials for innovative functional devices 用于创新功能器件的一维和二维纳米碳材料
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998195
Shintaro Sato
{"title":"One and two dimensional nanocarbon materials for innovative functional devices","authors":"Shintaro Sato","doi":"10.23919/VLSIT.2017.7998195","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998195","url":null,"abstract":"One and two dimensional nanocarbon (NC) materials, including carbon nanotubes (CNTs), graphene and graphene nanoribbons (GNRs) have excellent properties and can therefore be building blocks of future electronic devices. It has been predicted and demonstrated that transistor channels and interconnects (More Moore devices) made of NC materials have excellent properties [1-6]. NC-based Beyond CMOS and More than Moore (MtM) devices have also been proposed and demonstrated [6-10]. In this paper, we briefly review some of MtM or functional devices using NC materials, which include terahertz (THz) wave detectors, strain sensors, and gas sensors. A novel gas sensor based on a graphene-gate transistor we have recently developed [11] is also described.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130524259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability 降低接触电阻的双光束激光退火及其对VLSI集成电路可变性的影响
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998175
Zuoguang Liu, O. Gluschenkov, H. Niimi, Bei Liu, Juntao Li, J. Demarest, S. Mochizuki, P. Adusumilli, M. Raymond, A. Carr, Shaoyin Chen, Y. Wang, H. Jagannathan, T. Yamashita
{"title":"Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability","authors":"Zuoguang Liu, O. Gluschenkov, H. Niimi, Bei Liu, Juntao Li, J. Demarest, S. Mochizuki, P. Adusumilli, M. Raymond, A. Carr, Shaoyin Chen, Y. Wang, H. Jagannathan, T. Yamashita","doi":"10.23919/VLSIT.2017.7998175","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998175","url":null,"abstract":"Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with-in-die (WID Vt variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
First demonstration of diode-type 3-D NAND flash memory string having super-steep switching slope 具有超陡开关斜率的二极管型三维NAND闪存串的首次演示
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998172
Nagyong Choi, Ho-Jung Kang, Sungyong Chung, S. Bae, Byung-Gook Park, Jong-Ho Lee
{"title":"First demonstration of diode-type 3-D NAND flash memory string having super-steep switching slope","authors":"Nagyong Choi, Ho-Jung Kang, Sungyong Chung, S. Bae, Byung-Gook Park, Jong-Ho Lee","doi":"10.23919/VLSIT.2017.7998172","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998172","url":null,"abstract":"Super-steep switching is successfully demonstrated using positive feedback (PF) in fabricated diode-type 3-D NAND flash memory strings. Thanks to the PF, the subthreshold swing (SS) measured in a cell of a string during read operation is less than 1 mV/dec at turn-on voltage (Von) regardless of the polarity and the amount of the charge stored in the cell. This string has memory characteristics similar to conventional FET-type string while keeping much better SS than that of the FET-type string even after program/erase (P/E) cycling.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"25 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120869985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT 一款65nm 1.0 V 1.84 ns SOTB嵌入式SRAM,待机功率为13.72 nW/Mbit,适用于智能物联网
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008581
M. Yabuuchi, K. Nii, S. Tanaka, Y. Shinozaki, Yoshiki Yamamoto, T. Hasegawa, H. Shinkawata, S. Kamohara
{"title":"A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT","authors":"M. Yabuuchi, K. Nii, S. Tanaka, Y. Shinozaki, Yoshiki Yamamoto, T. Hasegawa, H. Shinkawata, S. Kamohara","doi":"10.23919/VLSIC.2017.8008581","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008581","url":null,"abstract":"A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125246930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Record low specific contact resistivity (1.2×10−9 Ω-cm2) for P-type semiconductors: Incorporation of Sn into Ge and in-Situ Ga doping p型半导体的低比接触电阻率(1.2×10−9 Ω-cm2): Sn掺入Ge和原位Ga掺杂
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998178
Ying Wu, Sheng Luo, Wei Wang, S. Masudy‐Panah, D. Lei, X. Gong, G. Liang, Y. Yeo
{"title":"Record low specific contact resistivity (1.2×10−9 Ω-cm2) for P-type semiconductors: Incorporation of Sn into Ge and in-Situ Ga doping","authors":"Ying Wu, Sheng Luo, Wei Wang, S. Masudy‐Panah, D. Lei, X. Gong, G. Liang, Y. Yeo","doi":"10.23919/VLSIT.2017.7998178","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998178","url":null,"abstract":"Record-low specific contact resistivity ρ<inf>c</inf> down to 1.2×10<sup>−9</sup> Ω-cm<sup>2</sup> is achieved for Ti/p<sup>+</sup>-Ge<inf>0.95</inf>Sn<inf>0.05</inf> contact by incorporating Sn into Ge and insitu Ga doping with active doping concentration of 1.6×10<sup>20</sup> cm<sup>−3</sup>. As compared with Ni(GeSn)/p<sup>+</sup>-Ge<inf>0.95</inf>Sn<inf>0.05</inf> contact, Ti/p<sup>+</sup>-Ge<inf>0.95</inf>Sn<inf>0.05</inf> contact exhibits lower ρ<inf>c</inf> and is more thermally stable. In addition, theoretical calculation shows that for a given doping concentration, incorporating Sn into Ge lowers the p<inf>c</inf> as compared with metal/p-Ge contacts.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Influence of stress induced CT local layout effect (LLE) on 14nm FinFET 应力诱导CT局部布局效应对14nm FinFET的影响
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998182
P. Zhao, S. Pandey, E. Banghart, Xiaoli He, R. Asra, V. Mahajan, Haojun Zhang, B. Zhu, Kenta Yamada, Linjun Cao, P. Balasubramaniam, M. Joshi, M. Eller, F. Benistant, S. Samavedam
{"title":"Influence of stress induced CT local layout effect (LLE) on 14nm FinFET","authors":"P. Zhao, S. Pandey, E. Banghart, Xiaoli He, R. Asra, V. Mahajan, Haojun Zhang, B. Zhu, Kenta Yamada, Linjun Cao, P. Balasubramaniam, M. Joshi, M. Eller, F. Benistant, S. Samavedam","doi":"10.23919/VLSIT.2017.7998182","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998182","url":null,"abstract":"In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125518612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998193
X. Sun, C. D'Emic, C. Cheng, A. Majumdar, Y. Sun, E. Cartier, R. Bruce, M. Frank, H. Miyazoe, K. Shiu, J. Rozen, J. Patel, T. Ando, W.-B. Song, M. Lofaro, M. Krishnan, B. Obrodovic, K. Lee, H. Tsai, W. Wang, W. Spratt, K. Chan, S. Lee, J. Yau, P. Hashemi, M. Khojasteh, M. Cantoro, J. Ott, T. Rakshit, Y. Zhu, D. Sadana, C. Yeh, V. Narayanan, R. Mo, Yeon-Cheol Heo, D-W. Kim, M. Rodder, E. Leobandung
{"title":"High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length","authors":"X. Sun, C. D'Emic, C. Cheng, A. Majumdar, Y. Sun, E. Cartier, R. Bruce, M. Frank, H. Miyazoe, K. Shiu, J. Rozen, J. Patel, T. Ando, W.-B. Song, M. Lofaro, M. Krishnan, B. Obrodovic, K. Lee, H. Tsai, W. Wang, W. Spratt, K. Chan, S. Lee, J. Yau, P. Hashemi, M. Khojasteh, M. Cantoro, J. Ott, T. Rakshit, Y. Zhu, D. Sadana, C. Yeh, V. Narayanan, R. Mo, Yeon-Cheol Heo, D-W. Kim, M. Rodder, E. Leobandung","doi":"10.23919/VLSIT.2017.7998193","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998193","url":null,"abstract":"We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127011855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A powerless and non-volatile counterfeit IC detection sensor in a standard logic process based on an exposed floating-gate array 一种基于暴露浮门阵列的标准逻辑过程中的无功率非易失伪造IC检测传感器
2017 Symposium on VLSI Technology Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998211
Muqing Liu, C. Kim
{"title":"A powerless and non-volatile counterfeit IC detection sensor in a standard logic process based on an exposed floating-gate array","authors":"Muqing Liu, C. Kim","doi":"10.23919/VLSIT.2017.7998211","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998211","url":null,"abstract":"Counterfeit ICs pose a threat to designing secure and reliable electronic systems. To better detect and prevent counterfeit ICs from entering the supply chain, an eflash based powerless non-volatile sensor using floating-gate (FG) technology is demonstrated in a 0.35μm standard logic process. By exposing the FG to the environment, the proposed sensor can record any physical tamper attempt affecting the charge stored on the exposed FG. Test results confirm that anomalous events such as temperature spikes, humidity changes, or increased dust particle density can be recorded by the sensor powerlessly, and later read out and analyzed whenever the power is available.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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