E. Hsieh, Y. C. Kuo, C. H. Cheng, J. L. Kuo, M. Jiang, J. L. Lin, H. W. Cheng, S. Chung, C. H. Liu, T. P. Chen, Y. H. Yeah, T. J. Chen, O. Cheng
{"title":"First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability","authors":"E. Hsieh, Y. C. Kuo, C. H. Cheng, J. L. Kuo, M. Jiang, J. L. Lin, H. W. Cheng, S. Chung, C. H. Liu, T. P. Chen, Y. H. Yeah, T. J. Chen, O. Cheng","doi":"10.23919/VLSIT.2017.7998204","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998204","url":null,"abstract":"For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET unit cell has been thoroughly investigated. To solve sneak path issue, a new active-fin-isolation (AFI) of FinFET in an AND-type array was proposed. This new AFI effectively increases the S/N margin of 103 and significantly reduces the standby power of 30% and active power of 99%, compared to original AND-type array. This work provides a promising candidate for the embedded FLASH memory on FinFET platform featuring fully-CMOS compatible integration and low cost solution in the more-than-Moore era.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Su, Y. Tang, Y.-C. Tsou, P. Sung, F. Hou, C. Wang, S.-T. Chung, Chen-Yi Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Yi-Ling Jian, T. Chou, Y.-L. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
{"title":"Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION","authors":"C. Su, Y. Tang, Y.-C. Tsou, P. Sung, F. Hou, C. Wang, S.-T. Chung, Chen-Yi Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Yi-Ling Jian, T. Chou, Y.-L. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.23919/VLSIT.2017.7998159","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998159","url":null,"abstract":"Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO<inf>x</inf> (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al<inf>2</inf>O<inf>3</inf> IL results in paraelectric behavior, HZO on GeO<inf>x</inf> IL exhibits significant FE. High I<inf>on</inf>/I<inf>off</inf> (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L<inf>g</inf>) of 60 nm and a FE-HZO/GeO<inf>x</inf> gate stack.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Record performance for junctionless transistors in InGaAs MOSFETs","authors":"C. Zota, M. Borg, L. Wernersson, E. Lind","doi":"10.23919/VLSIT.2017.7998190","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998190","url":null,"abstract":"We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In<inf>0.80</inf>Ga<inf>0.20</inf>As (N<inf>D</inf> ∼ 1×10<sup>19</sup> cm<sup>−3</sup>) as both channel and contacts. Devices with source and drain metal separation of 32 nm and L<inf>g</inf> of 25 nm exhibit SS = 76 mV/dec., both the highest reported g<inf>m</inf> = 1.6 mS/μΑ and I<inf>on</inf> = 160 μA/μm (V<inf>DD</inf> = 0.5 V, I<inf>OFF</inf> = 100 nA/μm) for a junctionless transistor. We also examine the influence of the contact thickness, comparing double-layer junctionless devices with 37 nm thick contacts with single-layer 7 nm contact devices.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125418400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Assaderaghi, Gowri Chindalore, Brima Ibrahim, Hans de Jong, M. Joye, Sami Nassar, Wolfgang Steinbauer, Mathias Wagner, Thomas Wille
{"title":"Privacy and security: Key requirements for sustainable IoT growth","authors":"F. Assaderaghi, Gowri Chindalore, Brima Ibrahim, Hans de Jong, M. Joye, Sami Nassar, Wolfgang Steinbauer, Mathias Wagner, Thomas Wille","doi":"10.23919/VLSIT.2017.7998185","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998185","url":null,"abstract":"As IoT moves beyond a catchphrase and starts to provide meaningful solutions in multiple fields, three of its critical pillars are now well understood: • Transducers are needed as means of interacting with the environment and machines, and in converting stimuli to data and vice versa. These sensors and actuators form the basis of contextual awareness. • Given that many end-node IoT devices are size and power constrained, local low-power computing is essential. The need for power-efficient end-node and edge computing becomes more apparent when latency, network bandwidth, and real time analytics are considered. • Low power communication links to transmit the data between IoT devices and local aggregators or cloud resources form the third pillar. Missing in this picture, and not fully appreciated yet, is the fourth pillar of IoT: privacy and security (P&S). If IoT is all about data, how P&S is treated will determine IoT's fate: a second phase of rapid proliferation or ultimate demise and collapse. Recent breaches in P&S are starting to change the industry's view on this issue. Even IoT end nodes that are low cost and have limited functionality pose significant risk to the entire system when their security is breached. This is due to the networking nature of the IoT that exposes a massive attack surface, making these devices ideal attack points for causing disruptions and stealing sensitive data. PC-era Internet security has been an expensive afterthought that has cost industry and consumers billions of dollars. Therefore, we should approach IoT differently, making P&S a key requirement at the design phase itself, and address all life-cycle aspects from initial deployment to in-field updates, to end-of-life decommissioning. This is a system level challenge that requires complete end-end HW/SW solutions, developed in partnership with the entire ecosystem.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Florent, S. Lavizzari, L. di Piazza, M. Popovici, E. Vecchio, G. Potoms, G. Groeseneken, J. Van IHoudt
{"title":"First demonstration of vertically stacked ferroelectric Al doped HfO2 devices for NAND applications","authors":"K. Florent, S. Lavizzari, L. di Piazza, M. Popovici, E. Vecchio, G. Potoms, G. Groeseneken, J. Van IHoudt","doi":"10.23919/VLSIT.2017.7998162","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998162","url":null,"abstract":"A 3D ferroelectric Al doped HfO2 device for NAND applications was fabricated for the first time. The polysilicon (poly-Si) channel, whose diameter ranges from 60 to 200 nm, was highly doped for a better understanding of the ferroelectric properties. Electrical results confirmed the presence of the ferroelectric phase with a coercive voltage (2Vc) of 6 V extracted from the hysteresis loop. The drain anneal was found to have a significant impact on HfO2 properties and needs to be reduced to preserve the ferroelectricity. Finally, reliability investigations showed an estimated time to failure of more than 10 years at 85 °C. This study lays the foundation for the fabrication of 3D ferroelectric field effect transistors (FeFET).","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131374471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hashimoto, Y. Kawabe, Michiharu Kara, Yasushi Kakimura, K. Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, H. Okano, Y. Tomita, S. Satoh, H. Yamashita
{"title":"An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors","authors":"T. Hashimoto, Y. Kawabe, Michiharu Kara, Yasushi Kakimura, K. Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, H. Okano, Y. Tomita, S. Satoh, H. Yamashita","doi":"10.23919/VLSIT.2017.7998133","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998133","url":null,"abstract":"This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive clocking control circuit with SPARC processor cores was fabricated in a 20-nm CMOS process. Experimental measurements demonstrated that the adaptive clocking control circuit achieved the state-of-the-art frequency gain of 7.5%, resulting in the operating frequency as high as 5 GHz.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124692622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Singh, A. Bousquet, J. Ciavatti, K. Sundaram, J. S. Wong, K. Chew, A. Bandyopadhyay, S. Li, A. Bellaouar, S. Pandey, B. Zhu, A. Martin, C. Kyono, J. Goo, H. Yang, A. Mehta, X. Zhang, O. Hu, S. Mahajan, E. Geiss, S. Yamaguchi, S. Mittal, R. Asra, P. M. Balasubramaniam, J. Watts, D. Harame, R. Todi, S. Samavedam, D. K. Sohn
{"title":"14nm FinFET technology for analog and RF applications","authors":"J. Singh, A. Bousquet, J. Ciavatti, K. Sundaram, J. S. Wong, K. Chew, A. Bandyopadhyay, S. Li, A. Bellaouar, S. Pandey, B. Zhu, A. Martin, C. Kyono, J. Goo, H. Yang, A. Mehta, X. Zhang, O. Hu, S. Mahajan, E. Geiss, S. Yamaguchi, S. Mittal, R. Asra, P. M. Balasubramaniam, J. Watts, D. Harame, R. Todi, S. Samavedam, D. K. Sohn","doi":"10.23919/VLSIT.2017.7998154","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998154","url":null,"abstract":"This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be seen in the self-gain (Gm/Gds), which shows a significant increase to 40 and 34 for NFET and PFET respectively. Superior 1/f noise of 17/35 f(V∗μm)2/Hz @ 1KHz for N/PFET respectively is also achieved. To extend further low voltage operation and power saving, ultra-low Vt devices are also developed. Furthermore, a deep N-well (triple well) process is introduced to improve the ultra-low signal immunity from substrate noise, while offering useful devices like VNPN and high breakdown voltage deep N-well diodes. A superior Ft/Fmax, high self-gain, low 1/f noise and substrate isolation characteristics truly extend the capability of the 14nm FinFETs for analog and RF applications.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121915840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Chang, T. Irisawa, H. Ishii, H. Hattori, H. Ota, H. Takagi, Y. Kurashima, N. Uchida, T. Maeda
{"title":"First experimental observation of channel thickness scaling (down to 3 nm) induced mobility enhancement in UTB GeOI nMOSFETs","authors":"W. Chang, T. Irisawa, H. Ishii, H. Hattori, H. Ota, H. Takagi, Y. Kurashima, N. Uchida, T. Maeda","doi":"10.23919/VLSIT.2017.7998167","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998167","url":null,"abstract":"Electron mobility of ultra thin body (UTB) GeOI «MOSFETs with body thickness (Tbody) down to 3 nm has been systematically investigated and significant mobility enhancement with decreasing Tbody has been observed for the first time. This channel thickness scaling induced mobility enhancement can be attributed to the unique physical property of ultra thin Ge where the electron effective mass reduces with scaling Tbody through the band structure modification.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122604492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, S. Slesazeck
{"title":"Novel ferroelectric FET based synapse for neuromorphic systems","authors":"H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller, P. Polakowski, T. Mikolajick, S. Slesazeck","doi":"10.23919/VLSIT.2017.7998165","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998165","url":null,"abstract":"A compact nanoscale device emulating the functionality of biological synapses is an essential element for neuromorphic systems. Here we present for the first time a synapse based on a single ferroelectric FET (FeFET) integrated in a 28nm HKMG technology, having hafnium oxide as the ferroelectric and a resistive element in series. The gradual and non-volatile ferroelectric switching is exploited to mimic the synaptic weight. We demonstrate both the spike-timing dependent plasticity (STDP) and the signal transmission and discuss the effect of the spike properties and circuit design on STDP.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129988934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sungsoo Choi, Kyungho Lee, Jung-Hyun Yun, Suyoung Choi, Seungjoon Lee, J. Park, E. Shim, J. Pyo, Bumsuk Kim, Minwook Jung, Yunki Lee, Kyungmok Son, Sangil Jung, Tae-Shick Wang, Yunseok Choi, D. Min, Joon-Hyuk Im, Changrok Moon, Duckhyung Lee, Duckhyun Chang
{"title":"An all pixel PDAF CMOS image sensor with 0.64μmx1.28μm photodiode separated by self-aligned in-pixel deep trench isolation for high AF performance","authors":"Sungsoo Choi, Kyungho Lee, Jung-Hyun Yun, Suyoung Choi, Seungjoon Lee, J. Park, E. Shim, J. Pyo, Bumsuk Kim, Minwook Jung, Yunki Lee, Kyungmok Son, Sangil Jung, Tae-Shick Wang, Yunseok Choi, D. Min, Joon-Hyuk Im, Changrok Moon, Duckhyung Lee, Duckhyun Chang","doi":"10.23919/VLSIT.2017.7998212","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998212","url":null,"abstract":"We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects and maximize the performance even at extremely low light condition up to 1lux. In particular the AF performance remains comparable to that of 0.70μm dual PD CIS. By using our unique technology, it seems plausible to scale further down the size of pixels in dual PD CIS without sacrificing AF performance.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116980757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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