C. Su, Y. Tang, Y.-C. Tsou, P. Sung, F. Hou, C. Wang, S.-T. Chung, Chen-Yi Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Yi-Ling Jian, T. Chou, Y.-L. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
{"title":"在特定界面层上采用低温铁电HfZrOx的纳米Ge finfet显示出65%的S.S.减少和离子的改善","authors":"C. Su, Y. Tang, Y.-C. Tsou, P. Sung, F. Hou, C. Wang, S.-T. Chung, Chen-Yi Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Yi-Ling Jian, T. Chou, Y.-L. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.23919/VLSIT.2017.7998159","DOIUrl":null,"url":null,"abstract":"Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO<inf>x</inf> (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al<inf>2</inf>O<inf>3</inf> IL results in paraelectric behavior, HZO on GeO<inf>x</inf> IL exhibits significant FE. High I<inf>on</inf>/I<inf>off</inf> (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L<inf>g</inf>) of 60 nm and a FE-HZO/GeO<inf>x</inf> gate stack.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION\",\"authors\":\"C. Su, Y. Tang, Y.-C. Tsou, P. Sung, F. Hou, C. Wang, S.-T. Chung, Chen-Yi Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Yi-Ling Jian, T. Chou, Y.-L. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang\",\"doi\":\"10.23919/VLSIT.2017.7998159\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO<inf>x</inf> (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al<inf>2</inf>O<inf>3</inf> IL results in paraelectric behavior, HZO on GeO<inf>x</inf> IL exhibits significant FE. High I<inf>on</inf>/I<inf>off</inf> (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L<inf>g</inf>) of 60 nm and a FE-HZO/GeO<inf>x</inf> gate stack.\",\"PeriodicalId\":333275,\"journal\":{\"name\":\"2017 Symposium on VLSI Technology\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2017.7998159\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2017.7998159","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results in paraelectric behavior, HZO on GeOx IL exhibits significant FE. High Ion/Ioff (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (Lg) of 60 nm and a FE-HZO/GeOx gate stack.
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