H. K. Park, K. W. Lee, S. -. Song, K. G. Lee, J. Shin, V. Gangasani, Y. S. Shin, D. Kang, J. H. Park, K. W. Song, G. Koh, G. Jeong, K. Park, K. Kyung
{"title":"A novel write method for improving RESET distribution of PRAM","authors":"H. K. Park, K. W. Lee, S. -. Song, K. G. Lee, J. Shin, V. Gangasani, Y. S. Shin, D. Kang, J. H. Park, K. W. Song, G. Koh, G. Jeong, K. Park, K. Kyung","doi":"10.23919/VLSIT.2017.7998209","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998209","url":null,"abstract":"RESET distribution of phase-change random access memory (PRAM) is highly related to heat fluctuations during RESET write (RESET<inf>W</inf>). In this work we investigate the effect of load resistance (R<inf>L</inf>) with constant voltage write method and propose new RESET<inf>W</inf> method with an optimal R<inf>L</inf> selection equation with considering Joule heating and thermoelectric effects. Since the optimal R<inf>L</inf> compensates for intrinsic dynamic resistance variation in PRAM, the heat fluctuation is reduced and the RESET distribution is improved. With fabricated PRAM TEG, we verify that optimal RL exists and achieve more improved RESET distribution with the optimized R<inf>L</inf> by 41% than with R<inf>L</inf> not optimized.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115811955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Loubet, T. Hook, P. Montanini, C. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, Xin He Miao, J. Wang, A. Young, R. Chao, M. Kang, Z. Liu, S. Fan, B. Hamieh, S. Sieg, Y. Mignot, W. Xu, S. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, Á. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, R. Wong, D. Brown, P. Oldiges, R. Robison, J. Arnold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M. Na, A. Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, M. Khare
{"title":"Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET","authors":"N. Loubet, T. Hook, P. Montanini, C. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, Xin He Miao, J. Wang, A. Young, R. Chao, M. Kang, Z. Liu, S. Fan, B. Hamieh, S. Sieg, Y. Mignot, W. Xu, S. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, Á. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, R. Wong, D. Brown, P. Oldiges, R. Robison, J. Arnold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M. Na, A. Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, M. Khare","doi":"10.23919/VLSIT.2017.7998183","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998183","url":null,"abstract":"In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128649615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Navarro, A. Verdy, N. Castellani, G. Bourgeois, V. Sousa, G. Molas, M. Bernard, C. Sabbione, P. Noé, J. Garrione, L. Fellouh, L. Perniola
{"title":"Innovative PCM+OTS device with high sub-threshold non-linearity for non-switching reading operations and higher endurance performance","authors":"G. Navarro, A. Verdy, N. Castellani, G. Bourgeois, V. Sousa, G. Molas, M. Bernard, C. Sabbione, P. Noé, J. Garrione, L. Fellouh, L. Perniola","doi":"10.23919/VLSIT.2017.7998208","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998208","url":null,"abstract":"In this paper we present the engineering of a non-volatile 1S1R memory based on a Phase-Change Memory cell (PCM), consisting in a GeN/Ge2Sb2Te5 layer, stacked with a GeSe-based Ovonic Threshold Switching selector device (OTS). We optimize and analyze separately the two devices, and we propose for the first time an innovative reading strategy of the cross point device, enabled by the improved sub-threshold non-linearity of the OTS selector. A new memory concept is presented and demonstrated in which selector switching is performed only for SET and RESET programming operations and reading is operated without switching the OTS selector, strategy that allows to target outstanding endurances.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114929643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Sharma, K. Tapily, A. Saha, J. Zhang, A. Shaughnessy, Ahmedullah Aziz, G. Snider, S. Gupta, R. Clark, S. Datta
{"title":"Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack","authors":"P. Sharma, K. Tapily, A. Saha, J. Zhang, A. Shaughnessy, Ahmedullah Aziz, G. Snider, S. Gupta, R. Clark, S. Datta","doi":"10.23919/VLSIT.2017.7998160","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998160","url":null,"abstract":"We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SSrev) below kT/q over four decades of drain current. Temperature dependent transport study shows that, the effective mobility of HZO NCFETs is 15 % higher than that of HfO2 based control MOSFETs due to suppression of Hf diffusion into the interfacial SiO2 layer (IL). Using the Preisach hysteresis model, which models dynamics of FE switching through a cluster of independent switching dipoles at arbitrary electric field, we (a) explain the asymmetric SS behavior of NCFETs in MFIS configuration, and (b) establish design guidelines for achieving sub-kT/q SS in both forward and reverse sweep direction.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124052264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Deshpande, H. Hahn, E. O'Connor, Y. Baumgartner, M. Sousa, D. Caimi, H. Boutry, J. Widiez, L. Brevard, C. Le Royer, M. Vinet, J. Fompeyrine, L. Czornomaz
{"title":"First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts","authors":"V. Deshpande, H. Hahn, E. O'Connor, Y. Baumgartner, M. Sousa, D. Caimi, H. Boutry, J. Widiez, L. Brevard, C. Le Royer, M. Vinet, J. Fompeyrine, L. Czornomaz","doi":"10.23919/VLSIT.2017.7998205","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998205","url":null,"abstract":"We demonstrate, for the first time, the 3D Monolithic (3DM) integration of In0.53GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFETs on the top layer and Gate-First Si CMOS on the bottom layer with TiN/W inter-layer contacts. State-of-the-art device integration is achieved with the top layer InGaAs utilizing raised source drain (RSD) and the bottom layer CMOS having Si RSD for nFETs, SiGe RSD for pFETs, implants, silicide and TiN/W plug contacts. The top layer InGaAs n-FinFETs are scaled down to Lg =25 nm and both the Si nFETs and pFETs in the bottom layer are scaled down to Lg ∼15 nm. Finally, utilizing the inter-layer contacts, we demonstrate a densely integrated 3D 6T-SRAM circuit with InGaAs nFETs stacked on top of Si pFETs showing considerable area reduction with respect to a 2D layout.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Ha, C. Yang, J. Lee, S. Lee, S. Lee, K. Seo, H. Oh, E. Hwang, S. Do, S. Park, M. Sun, D. H. Kim, J. Lee, M. Kang, S.-S. Ha, D. Choi, H. Jun, H. J. Shin, Y. Kim, C. Moon, Y. W. Cho, S. H. Park, Y. Son, J. Park, B. C. Lee, C. Kim, Y. Oh, J. S. Park, S. Kim, M. Kim, K. Hwang, S. Nam, S. Maeda, D.-W. Kim, J. Lee, M. Liang, E. Jung
{"title":"Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications","authors":"D. Ha, C. Yang, J. Lee, S. Lee, S. Lee, K. Seo, H. Oh, E. Hwang, S. Do, S. Park, M. Sun, D. H. Kim, J. Lee, M. Kang, S.-S. Ha, D. Choi, H. Jun, H. J. Shin, Y. Kim, C. Moon, Y. W. Cho, S. H. Park, Y. Son, J. Park, B. C. Lee, C. Kim, Y. Oh, J. S. Park, S. Kim, M. Kim, K. Hwang, S. Nam, S. Maeda, D.-W. Kim, J. Lee, M. Liang, E. Jung","doi":"10.23919/VLSIT.2017.7998202","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998202","url":null,"abstract":"7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"166 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Lei, K. Lee, Shuyu Bao, Wei Wang, S. Masudy‐Panah, S. Yadav, Annie Kumar, Yuan Dong, Yuye Kang, Shengqiang Xu, Ying Wu, Yi-Chiau Huang, Hua Chung, S. Chu, S. Kuppurao, C. S. Tan, X. Gong, Y. Yeo
{"title":"The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs","authors":"D. Lei, K. Lee, Shuyu Bao, Wei Wang, S. Masudy‐Panah, S. Yadav, Annie Kumar, Yuan Dong, Yuye Kang, Shengqiang Xu, Ying Wu, Yi-Chiau Huang, Hua Chung, S. Chu, S. Kuppurao, C. S. Tan, X. Gong, Y. Yeo","doi":"10.23919/VLSIT.2017.7998170","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998170","url":null,"abstract":"The world's first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths L<inf>ch</inf> down to 50 nm and fin width W<inf>Fin</inf> down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high G<inf>m, int</inf>, of 807 μS/um (VDs of −0.5 V), and the highest G<inf>m, int</inf>/S<inf>sat</inf>, were achieved. The highest high-field hole mobility of 208 cm2/Vs (at inversion carrier density of 8×10<sup>−2</sup> cm<sup>−2</sup>) for GeSn p-FETs with CVD grown GeSn channel was also obtained.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121901958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scaling, stacking, and printing: How 1D and 2D nanomaterials still hold promise for a new era of electronics","authors":"A. Franklin","doi":"10.23919/VLSIT.2017.7998194","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998194","url":null,"abstract":"1D and 2D nanomaterials continue to show promise for use in electronic devices. Their atomically thin size and superb transport properties make them of great value for transistors scaled in size and, more importantly, in voltage. Meanwhile, their substrate independence and van der Waals nature allows for ready stacking of nanomaterials at the device (interdigitated channels) or chip (monolithic 3D integrated) level. Finally, with dispersion into solution-phase inks, nanomaterials can be printed into thin-film devices for a new era of low-cost, flexible electronics that outperform competing printable materials. Each of these areas — scaling, stacking, and printing — benefit from uniquely from nanomaterials and will be reviewed herein.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Witters, F. Sebaai, A. Hikavyy, A. Milenin, R. Loo, A. De Keersgieter, G. Eneman, T. Schram, K. Wostyn, K. Devriendt, A. Schulze, R. Lieten, S. Bilodeau, E. Cooper, P. Storck, C. Vrancken, H. Arimura, P. Favia, E. Vancoille, J. Mitard, R. Langer, A. Opdebeeck, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert
{"title":"Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition","authors":"L. Witters, F. Sebaai, A. Hikavyy, A. Milenin, R. Loo, A. De Keersgieter, G. Eneman, T. Schram, K. Wostyn, K. Devriendt, A. Schulze, R. Lieten, S. Bilodeau, E. Cooper, P. Storck, C. Vrancken, H. Arimura, P. Favia, E. Vancoille, J. Mitard, R. Langer, A. Opdebeeck, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert","doi":"10.23919/VLSIT.2017.7998168","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998168","url":null,"abstract":"Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133421701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ohmori, A. Shinoda, K. Kawai, Z. Wei, T. Mikawa, R. Hasunuma
{"title":"Reduction of cycle-to-cycle variability in ReRAM by filamentary refresh","authors":"K. Ohmori, A. Shinoda, K. Kawai, Z. Wei, T. Mikawa, R. Hasunuma","doi":"10.23919/VLSIT.2017.7998206","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998206","url":null,"abstract":"In this paper, we clarify a filamentary “refresh” mechanism of a resistive random access memory (ReRAM) cell. Based on this mechanism, we propose an intentional refresh introduction that enables a reduction in the standard deviation (σ) of current values. The activation energy (E<inf>A</inf>) associated with oxygen vacancies (V<inf>o</inf>s) in ReRAM was investigated using low-frequency-noise spectroscopy, revealing continuous variation of E<inf>a</inf>.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123413986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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