An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

Abstract

This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive clocking control circuit with SPARC processor cores was fabricated in a 20-nm CMOS process. Experimental measurements demonstrated that the adaptive clocking control circuit achieved the state-of-the-art frequency gain of 7.5%, resulting in the operating frequency as high as 5 GHz.