Sam Yang, Yanxiang Liu, M. Cai, Jerry Bao, P. Feng, Xiangdong Chen, L. Ge, Jun Yuan, Jihong Choi, Ping Liu, Youseok Suh, Hao Wang, Jie Deng, Yandong Gao, Jackie Yang, Xiao-Yong Wang, Dang-qiang Yang, John Zhu, P. Pénzes, S. C. Song, Chulyong Park, Sungwon Kim, Jedon D. Kim, S. Kang, E. Terzioglu, K. Rim, P. Chidambaram
{"title":"10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling","authors":"Sam Yang, Yanxiang Liu, M. Cai, Jerry Bao, P. Feng, Xiangdong Chen, L. Ge, Jun Yuan, Jihong Choi, Ping Liu, Youseok Suh, Hao Wang, Jie Deng, Yandong Gao, Jackie Yang, Xiao-Yong Wang, Dang-qiang Yang, John Zhu, P. Pénzes, S. C. Song, Chulyong Park, Sungwon Kim, Jedon D. Kim, S. Kang, E. Terzioglu, K. Rim, P. Chidambaram","doi":"10.23919/VLSIT.2017.7998203","DOIUrl":null,"url":null,"abstract":"The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2017.7998203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.
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