R. Berthelon, F. Andneu, F. Triozon, M. Cassé, L. Bourdet, G. Ghibaudo, D. Rideau, Y. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet
{"title":"Impact of strain on access resistance in planar and nanowire CMOS devices","authors":"R. Berthelon, F. Andneu, F. Triozon, M. Cassé, L. Bourdet, G. Ghibaudo, D. Rideau, Y. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet","doi":"10.23919/VLSIT.2017.7998180","DOIUrl":null,"url":null,"abstract":"We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R<inf>ACC</inf>) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R<inf>acc</inf> (−21% for 4 V V<inf>b</inf> and −53% for −1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε<inf>n/p</inf>=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.","PeriodicalId":333275,"journal":{"name":"2017 Symposium on VLSI Technology","volume":"395 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2017.7998180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (RACC) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on Racc (−21% for 4 V Vb and −53% for −1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under εn/p=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.
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