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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge TinyVers:一个0.8-17 TOPS/W, 1.7 μW-20 mW，具有状态保留eMRAM的微型通用片上系统，用于极端边缘的机器学习推理
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830409
V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst
{"title":"TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge","authors":"V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst","doi":"10.1109/vlsitechnologyandcir46769.2022.9830409","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830409","url":null,"abstract":"This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip (SoC) to bring enhanced intelligence to the Extreme Edge. TinyVers exploits dataflow flexibility for multi-model support, and aggressive on-chip power management optimized for Extreme Edge smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W flexible ML accelerator with block structured sparsity support and efficient zero-skipping for deconvolution, a 1.7 μW deep sleep wake-up controller and an eMRAM for non-volatile storage, to perform up to 17.6 GOPS while achieving a power range from 1.7 μW-20 mW. Multiple ML models for diverse applications are mapped to show the flexibility and energy efficiency of the SoC with all models achieving 1-2 TOPS/W at less than 230 μW power for continuous operation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125245746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator 带占空比积分器的一阶连续时间噪声整形SAR ADC
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830373
Hanyue Li, Yuting Shen, E. Cantatore, P. Harpe
{"title":"A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator","authors":"Hanyue Li, Yuting Shen, E. Cantatore, P. Harpe","doi":"10.1109/vlsitechnologyandcir46769.2022.9830373","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830373","url":null,"abstract":"This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 μW, and it provides 15 dB anti-aliasing in the alias band.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition 用于神经信号采集的128通道交流耦合一阶Δ-Δ∑IC
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830236
Xiaolin Yang, M. Ballini, C. Sawigun, Wen-Yang Hsu, J. Weijers, J. Putzeys, C. Lopez
{"title":"A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition","authors":"Xiaolin Yang, M. Ballini, C. Sawigun, Wen-Yang Hsu, J. Weijers, J. Putzeys, C. Lopez","doi":"10.1109/vlsitechnologyandcir46769.2022.9830236","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830236","url":null,"abstract":"In this paper, we present a miniature 128-channel neural recording IC (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs). An AC-coupled 1st-order Δ-ΔΣ architecture is proposed to achieve rail-to-rail electrode DC offset rejection, low power and small area, while providing low noise and larger input range compared to other AC-coupled designs. This digitally-intensive architecture leverages the advantages of a highly-scaled technology node (22nm FD-SOI). The fabricated NRIC achieves a total area per channel of 0.005mm2, a total power per channel of 8.3μW, and an input-referred noise of 7.7±0.4μVrms in the AP band and 11.9±1.1μVrms in the LFP band. The chip has been fully validated in saline, demonstrating its capability to successfully record full-band neural signals.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122651616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 4K–400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer 4K-400K宽工作温度范围MRAM技术，超薄复合自由层和镁间隔层
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830503
Ming-Chun Hong, Yao-Jen Chang, Y. Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I. Wang, S. Z. Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, S. Sheu, W. Lo, Minn-Tsong Lin, Chih-I Wu, T. Hou
{"title":"A 4K–400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer","authors":"Ming-Chun Hong, Yao-Jen Chang, Y. Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I. Wang, S. Z. Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, S. Sheu, W. Lo, Minn-Tsong Lin, Chih-I Wu, T. Hou","doi":"10.1109/vlsitechnologyandcir46769.2022.9830503","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830503","url":null,"abstract":"A universal MRAM technology is proposed to fulfill versatile applications ranging from quantum computing to automotive electronics across a wide operating temperature range of 4K to 400K. An ultrathin (1.4 nm) CoFeB composite free layer with an Mg spacer is designed to enlarge breakdown voltage and write margin, decrease switching current, and maintain thermal stability and magnetoresistance ratio at all temperatures. High endurance (>1011) and excellent reliability (write margin > 0.4 V) are achieved from 4K to 400K without compromising speed (10 ns) and retention (10 years at 300K).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122708794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter 可编程物质中用于静电驱动的286nW, 103V高压发生器和多路复用器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830205
Yimai Peng, G. Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, J. Bourgeois, D. Blaauw, D. Sylvester
{"title":"A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter","authors":"Yimai Peng, G. Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, J. Bourgeois, D. Blaauw, D. Sylvester","doi":"10.1109/vlsitechnologyandcir46769.2022.9830205","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830205","url":null,"abstract":"We present a high-voltage-generation-and-multiplexing (HVGM) chip, specifically designed for electrostatic actuation of micro-robots. It can individually control 12 pairs of +/- electrodes using a positive and negative charge pump and mux-structure, consumes 286nW in steady state and 533nW when transitioning a 10pF electrode at 155V/s, and produces a differential voltage of 103V (29× voltage gain from 3.6V) in measurement. We also show a complete microsystem of stacked die, measuring 3×1.4×1.1mm, including HVGM, processor, radio, and harvester for energy autonomous operation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131263051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 100×80 CMOS Flash LiDAR Sensor with 0.0011mm2 In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADC 基于模拟计数器和自校准单斜率ADC的0.0011mm2像素直方图TDC 100×80 CMOS Flash LiDAR传感器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830305
Su Han, Bumjun Kim, Seonghyeok Park, Yongjae Park, J. Chun, Jaehyuk Choi, Seong-Jin Kim
{"title":"A 100×80 CMOS Flash LiDAR Sensor with 0.0011mm2 In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADC","authors":"Su Han, Bumjun Kim, Seonghyeok Park, Yongjae Park, J. Chun, Jaehyuk Choi, Seong-Jin Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830305","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830305","url":null,"abstract":"This paper presents a CMOS flash LiDAR sensor with an in-pixel histogramming TDC occupying the smallest size of 1110μm2 based on dual analog counters. The proposed analog counter replaced with histogram memories achieves 3,300-fold power reduction compared with the conventional digital counter. The analog counters and a timing generator in each pixel are reconfigured to a single-slope ADC (SS-ADC) with a self-referenced ramp mitigating nonuniformities of counters. The prototype LiDAR sensor fabricated in a 0.11µm CMOS process demonstrates a 2.3cm depth resolution at a 7.5m distance. An analog counter only consumes 8nW for in-pixel histogramming operation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131486436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine 基于8位20.7 TOPS/W多级Cell reram的计算引擎
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830490
Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, N. Breil, R. Quon, D. Kamalanathan, Siddarth A. Krishnan, M. Chudzik, Zhengya Zhang, W. Lu, M. Flynn
{"title":"An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine","authors":"Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, N. Breil, R. Quon, D. Kamalanathan, Siddarth A. Krishnan, M. Chudzik, Zhengya Zhang, W. Lu, M. Flynn","doi":"10.1109/vlsitechnologyandcir46769.2022.9830490","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830490","url":null,"abstract":"Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%) 具有高外量子效率(bbb70 %)的亚微米厚InGaAs宽带(400-1700 nm)光电探测器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830388
Dae-Myeong Geum, Jinha Lim, Ju-Hwan Jang, Seungyeop Ahn, S. Kim, J. Shim, Bong-Ho Kim, Juhyuk Park, Woojin Baek, Jaeyong Jeong, Sanghyeon Kim
{"title":"A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%)","authors":"Dae-Myeong Geum, Jinha Lim, Ju-Hwan Jang, Seungyeop Ahn, S. Kim, J. Shim, Bong-Ho Kim, Juhyuk Park, Woojin Baek, Jaeyong Jeong, Sanghyeon Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830388","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830388","url":null,"abstract":"A sub-micron-thick InGaAs photodetectors (PDs) with a broad spectrum coverage (400-1700 nm) and high external quantum efficiency (EQE) (>70%) were successfully demonstrated through guided-mode resonance structure and surface layer thinning process. It showed the outstanding EQE of 83.8%, and 65.5% at 1000 nm, 1550 nm for 500-nm-thick InGaAs absorption layer, respectively. Compared to previous results, thickness reduction by 6.8 times and comparable QE were simultaneously achieved.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132569709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays 具有子阵列间脉宽调制的40nm模拟输入无adc内存中计算RRAM宏
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830211
Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
{"title":"A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays","authors":"Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830211","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830211","url":null,"abstract":"This paper presents an ADC-free compute-in-memory (CIM) RRAM-based macro, exploiting the fully analog intra-/inter-array computation. The main contributions include: 1) a lightweight input-encoding scheme based on pulse-width modulation (PWM), which improves the compute throughput by ~7 times; 2) a fully analog data processing manner between sub-arrays without explicit ADCs, which does not introduce quantization loss and saves the power by a factor of 11.6. The 40nm prototype chip with TSMC RRAM achieves energy efficiency of 421.53 TOPS/W and compute efficiency of 360 GOPS/mm2 (normalized to binary operation) at 100MHz.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133196213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process 基于fll的5nm FINFET安全电路时钟故障检测器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830157
Sanquan Song, S. Tell, B. Zimmer, Sudhir S. Kudva, N. Nedovic, C. T. Gray
{"title":"An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process","authors":"Sanquan Song, S. Tell, B. Zimmer, Sudhir S. Kudva, N. Nedovic, C. T. Gray","doi":"10.1109/vlsitechnologyandcir46769.2022.9830157","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830157","url":null,"abstract":"The rapid complexity growth of electronic systems nowadays increases their vulnerability to hacking, such as fault injection, including insertion of glitches into the system clock to corrupt internal state through timing errors. As a countermeasure, a frequency locked loop (FLL) based clock glitch detector is proposed in this paper. Regulated from an external supply voltage, this FLL locks at 16-36X of the system clock, creating four phases to measure the system clock by oversampling at 64-144X. The samples are then used to sense the frequency and close the frequency locked loop, as well as to detect glitches through pattern matching. Implemented in a 5nm FINFET process, it can detect the glitches or pulse width variations down to 3.125% of the input 40MHz clock cycle with the supply varying from 0.5 to 1.0V.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133491824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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