Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, N. Breil, R. Quon, D. Kamalanathan, Siddarth A. Krishnan, M. Chudzik, Zhengya Zhang, W. Lu, M. Flynn
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An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine
Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.
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