V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst
{"title":"TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge","authors":"V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst","doi":"10.1109/vlsitechnologyandcir46769.2022.9830409","DOIUrl":null,"url":null,"abstract":"This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip (SoC) to bring enhanced intelligence to the Extreme Edge. TinyVers exploits dataflow flexibility for multi-model support, and aggressive on-chip power management optimized for Extreme Edge smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W flexible ML accelerator with block structured sparsity support and efficient zero-skipping for deconvolution, a 1.7 μW deep sleep wake-up controller and an eMRAM for non-volatile storage, to perform up to 17.6 GOPS while achieving a power range from 1.7 μW-20 mW. Multiple ML models for diverse applications are mapped to show the flexibility and energy efficiency of the SoC with all models achieving 1-2 TOPS/W at less than 230 μW power for continuous operation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830409","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip (SoC) to bring enhanced intelligence to the Extreme Edge. TinyVers exploits dataflow flexibility for multi-model support, and aggressive on-chip power management optimized for Extreme Edge smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W flexible ML accelerator with block structured sparsity support and efficient zero-skipping for deconvolution, a 1.7 μW deep sleep wake-up controller and an eMRAM for non-volatile storage, to perform up to 17.6 GOPS while achieving a power range from 1.7 μW-20 mW. Multiple ML models for diverse applications are mapped to show the flexibility and energy efficiency of the SoC with all models achieving 1-2 TOPS/W at less than 230 μW power for continuous operation.