TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge

V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst
{"title":"TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge","authors":"V. Jain, J. S. P. Giraldo, Jaro De Roose, B. Boons, L. Mei, M. Verhelst","doi":"10.1109/vlsitechnologyandcir46769.2022.9830409","DOIUrl":null,"url":null,"abstract":"This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip (SoC) to bring enhanced intelligence to the Extreme Edge. TinyVers exploits dataflow flexibility for multi-model support, and aggressive on-chip power management optimized for Extreme Edge smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W flexible ML accelerator with block structured sparsity support and efficient zero-skipping for deconvolution, a 1.7 μW deep sleep wake-up controller and an eMRAM for non-volatile storage, to perform up to 17.6 GOPS while achieving a power range from 1.7 μW-20 mW. Multiple ML models for diverse applications are mapped to show the flexibility and energy efficiency of the SoC with all models achieving 1-2 TOPS/W at less than 230 μW power for continuous operation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830409","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip (SoC) to bring enhanced intelligence to the Extreme Edge. TinyVers exploits dataflow flexibility for multi-model support, and aggressive on-chip power management optimized for Extreme Edge smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W flexible ML accelerator with block structured sparsity support and efficient zero-skipping for deconvolution, a 1.7 μW deep sleep wake-up controller and an eMRAM for non-volatile storage, to perform up to 17.6 GOPS while achieving a power range from 1.7 μW-20 mW. Multiple ML models for diverse applications are mapped to show the flexibility and energy efficiency of the SoC with all models achieving 1-2 TOPS/W at less than 230 μW power for continuous operation.
TinyVers:一个0.8-17 TOPS/W, 1.7 μW-20 mW,具有状态保留eMRAM的微型通用片上系统,用于极端边缘的机器学习推理
本文介绍了TinyVers,这是一款微型多功能超低功耗机器学习片上系统(SoC),可为Extreme Edge带来增强的智能。TinyVers利用多模型支持的数据流灵活性,以及针对Extreme Edge智能传感应用优化的积极的片上电源管理。SoC结合了RISC-V主机处理器,17 TOPS/W灵活的ML加速器(具有块结构稀疏性支持和高效的零跳变反褶积),1.7 μW深度睡眠唤醒控制器和用于非易失性存储的eMRAM,可执行高达17.6 GOPS,同时实现1.7 μW-20 mW的功率范围。针对不同应用的多个ML模型映射,以显示SoC的灵活性和能效,所有模型在低于230 μW的功率下实现1-2 TOPS/W的连续运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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