用于神经信号采集的128通道交流耦合一阶Δ-Δ∑IC

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830236

Xiaolin Yang, M. Ballini, C. Sawigun, Wen-Yang Hsu, J. Weijers, J. Putzeys, C. Lopez

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引用次数: 6

摘要

在本文中，我们提出了一个微型128通道神经记录IC (NRIC)，用于同时采集局部场电位(LFPs)和动作电位(APs)。本文提出了一种交流耦合一阶Δ-ΔΣ架构，以实现轨对轨电极直流偏置抑制、低功耗和小面积，同时与其他交流耦合设计相比提供低噪声和更大的输入范围。这种数字密集型架构充分利用了高规模技术节点(22nm FD-SOI)的优势。所制备的NRIC每通道的总面积为0.005mm2，每通道的总功率为8.3μW, AP波段的输入参考噪声为7.7±0.4μVrms, LFP波段的输入参考噪声为11.9±1.1μVrms。该芯片已经在生理盐水中进行了充分验证，证明了其成功记录全频段神经信号的能力。

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A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition

In this paper, we present a miniature 128-channel neural recording IC (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs). An AC-coupled 1st-order Δ-ΔΣ architecture is proposed to achieve rail-to-rail electrode DC offset rejection, low power and small area, while providing low noise and larger input range compared to other AC-coupled designs. This digitally-intensive architecture leverages the advantages of a highly-scaled technology node (22nm FD-SOI). The fabricated NRIC achieves a total area per channel of 0.005mm2, a total power per channel of 8.3μW, and an input-referred noise of 7.7±0.4μVrms in the AP band and 11.9±1.1μVrms in the LFP band. The chip has been fully validated in saline, demonstrating its capability to successfully record full-band neural signals.

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来源期刊

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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