具有子阵列间脉宽调制的40nm模拟输入无adc内存中计算RRAM宏

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830211

Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu

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引用次数: 16

摘要

本文提出了一种无adc的内存计算(CIM)基于rram的宏，利用了完全模拟的阵列内/阵列间计算。主要贡献包括:1)基于脉宽调制(PWM)的轻量级输入编码方案，使计算吞吐量提高了约7倍;2)子阵列间的全模拟数据处理方式，无显式adc，不引入量化损耗，功耗节省11.6倍。采用台积电RRAM的40nm原型芯片在100MHz下的能量效率为421.53 TOPS/W，计算效率为360 GOPS/mm2(归一化到二进制运算)。

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A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays

This paper presents an ADC-free compute-in-memory (CIM) RRAM-based macro, exploiting the fully analog intra-/inter-array computation. The main contributions include: 1) a lightweight input-encoding scheme based on pulse-width modulation (PWM), which improves the compute throughput by ~7 times; 2) a fully analog data processing manner between sub-arrays without explicit ADCs, which does not introduce quantization loss and saves the power by a factor of 11.6. The 40nm prototype chip with TSMC RRAM achieves energy efficiency of 421.53 TOPS/W and compute efficiency of 360 GOPS/mm2 (normalized to binary operation) at 100MHz.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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