带占空比积分器的一阶连续时间噪声整形SAR ADC

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830373

Hanyue Li, Yuting Shen, E. Cantatore, P. Harpe

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引用次数: 4

摘要

本文提出了第一个连续时间(CT)噪声整形SAR (NS-SAR) ADC。与文献中先前的离散时间(DT) NS-SAR ADC不同，该ADC利用CT Gm-C积分器实现固有的抗混叠功能。为了解决dt操作的SAR ADC与CT积分器的时序冲突问题，将SAR ADC的采样开关去掉，使积分器占空比。该原型电路采用65 nm CMOS工艺，在62.5 kHz带宽内实现了77 dB的峰值SNDR，功耗为13.5 μW，在混叠频段提供了15 dB的抗混叠性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator

This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 μW, and it provides 15 dB anti-aliasing in the alias band.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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