发布求助
文献互助 智能选刊 最新文献

Proceedings of 4th Great Lakes Symposium on VLSI最新文献

筛选
英文 中文
Delay independent initialization of sequential circuits 顺序电路的延迟独立初始化
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289964
T. Chakraborty, V. Agrawal
{"title":"Delay independent initialization of sequential circuits","authors":"T. Chakraborty, V. Agrawal","doi":"10.1109/GLSV.1994.289964","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289964","url":null,"abstract":"We show that a given initialization sequence for a synchronous sequential circuit is not guaranteed to work correctly when arbitrary path delays are present in the circuit. In this paper, we present a novel robust-initialization procedure for sequential circuits. This procedure guarantees the correct initialization of state elements of a sequential circuit regardless of delays in the circuit. Every pattern of the normal initialization sequence is repeatedly clocked in flip-flops, so that excessive delays on combinational paths feeding flip-flops do not prevent the proper initialization. This method guarantees the correct initialization of pipeline circuits. For a general sequential circuit which may have feedbacks, we give a simulation procedure to determine the initial state of the circuit that is guaranteed to be correct for arbitrarily large but bounded delays.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124023177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient simulation of switch-level circuits in a hierarchical simulation environment 在分层仿真环境中实现开关级电路的高效仿真
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289963
J. Wehbeh, D. Saab
{"title":"Efficient simulation of switch-level circuits in a hierarchical simulation environment","authors":"J. Wehbeh, D. Saab","doi":"10.1109/GLSV.1994.289963","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289963","url":null,"abstract":"Switch-level simulation provides a good level of abstraction for simulating digital MOS circuits. For handling large circuits, it is often necessary to represent parts of the circuit by high-level software models, in order to speed up the simulation process. This paper, considers hierarchical switch-level circuits, and investigates the use of extracted functional models at different levels in the hierarchy to increase the efficiency of simulation. A comparative study, on some sample circuits, is used to determine the ideal size of a module that should be simulated using its functional model.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130815045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Convergence analyses of simulated evolution algorithms 模拟进化算法的收敛性分析
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290000
Chi-Yu Mao, Y. Hu
{"title":"Convergence analyses of simulated evolution algorithms","authors":"Chi-Yu Mao, Y. Hu","doi":"10.1109/GLSV.1994.290000","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290000","url":null,"abstract":"In this paper, we show that simulated evolution (SE) can be modeled by an ergodic Markov chain. As such, the global convergence of the SE algorithm is established. Moreover, we propose to use the mean first visit time of an ergodic Markov chain to characterize the convergence time of the SE algorithm such that the fast convergence feature of SE can be assessed theoretically and experimentally.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114221641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mapping tensor products onto VLSI networks with reduced I/O 映射张量产品到VLSI网络与减少I/O
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289978
A. Elnaggar, H. Alnuweiri, M. Ito
{"title":"Mapping tensor products onto VLSI networks with reduced I/O","authors":"A. Elnaggar, H. Alnuweiri, M. Ito","doi":"10.1109/GLSV.1994.289978","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289978","url":null,"abstract":"This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT/sup 2/ trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Symbolic traversals of data paths with auxiliary variables 带辅助变量的数据路径的符号遍历
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289989
G. Cabodi, P. Camurati, S. Quer
{"title":"Symbolic traversals of data paths with auxiliary variables","authors":"G. Cabodi, P. Camurati, S. Quer","doi":"10.1109/GLSV.1994.289989","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289989","url":null,"abstract":"Symbolic state space traversal techniques are best on control-dominated circuits, not on data paths. This paper extends their applicability to regular structures commonly found in data paths by using auxiliary variables to decompose and to manipulate Boolean functions in decomposed form. Experimental results demonstrate the gain both in terms of binary decision diagram (BDD) size and CPU time.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124930641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power differential CML and ECL BiCMOS circuit techniques 低功耗差分CML和ECL BiCMOS电路技术
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289967
K. Sharaf, M. Elmasry
{"title":"Low-power differential CML and ECL BiCMOS circuit techniques","authors":"K. Sharaf, M. Elmasry","doi":"10.1109/GLSV.1994.289967","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289967","url":null,"abstract":"The performance of the different two-level series-gated CML BiCMOS schemes has been studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, have shown an improvement of 42% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating an the low power regime (<1 mW). Moreover, the BJT-MOS frequency divider configuration exhibits a high input sensitivity throughout the frequency range of operation. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115321279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications 设计了一种适用于线性收缩阵列DSP的容错GEQRNS处理单元
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289997
Jermy C. Smith, F. Taylor
{"title":"The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications","authors":"Jermy C. Smith, F. Taylor","doi":"10.1109/GLSV.1994.289997","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289997","url":null,"abstract":"In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123142368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Simulated annealing based yield enhancement of layouts 基于模拟退火的版图良率提高
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289975
R. Karri, A. Orailoglu
{"title":"Simulated annealing based yield enhancement of layouts","authors":"R. Karri, A. Orailoglu","doi":"10.1109/GLSV.1994.289975","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289975","url":null,"abstract":"This paper presents DEFT, a system for synthesizing defect-tolerant layouts, that in-grains tolerance to fabrication induced defects. This is accomplished by dispersing nets with large overlaps into nonadjacent tracks. DEFT also affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by DEFT have been consistently superior to those generated by other layout synthesis systems.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new systolic architecture for pipeline prime factor DFT-algorithm 管道素因子dft算法的一种新的收缩结构
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289998
S. Sedukhin
{"title":"A new systolic architecture for pipeline prime factor DFT-algorithm","authors":"S. Sedukhin","doi":"10.1109/GLSV.1994.289998","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289998","url":null,"abstract":"The paper shows how a rectangular array of N=N/sub 1spl times/N/sub 2/ processing elements (PE), where N/sub 1/ and N/sub 2/ are relatively prime, can be used do carry out efficient two-dimensional systolic implementation of N-point DFT, offering highly attractive throughput rates in relation to other N-processor solutions, such as the conventional linear systolic array. The systematic approach allows one to choose, among all possible systolic processors for the 2D-DFT algorithm, an optimal design which has the minimum number of locally connected PE's, good coordination between the processes of computation and communication, a small number of I/O pins, the minimum possible time of processing and the minimum amount of input data.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123924339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
FPGA-based synthesis of FSMs through decomposition 基于fpga的分解合成fsm
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289988
Wen-Lin Yang, R. Owens, M. J. Irwin
{"title":"FPGA-based synthesis of FSMs through decomposition","authors":"Wen-Lin Yang, R. Owens, M. J. Irwin","doi":"10.1109/GLSV.1994.289988","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289988","url":null,"abstract":"In this paper, we present a heuristic to synthesize a finite state machine as a set of smaller interacting submachines based on FPGA technology. This heuristic partitions inputs as well as outputs. Experimental results show that the sizes of submachines are much smaller than the size of original machine. As a result, the distributed smaller submachines can be operated faster than the original machine because of shorter critical paths.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信