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Proceedings of 4th Great Lakes Symposium on VLSI最新文献

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Generation of color-constrained spanning trees with application in symbolic circuit analysis 颜色约束生成树的生成及其在符号电路分析中的应用
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289959
Qicheng Yu, C. Sechen
{"title":"Generation of color-constrained spanning trees with application in symbolic circuit analysis","authors":"Qicheng Yu, C. Sechen","doi":"10.1109/GLSV.1994.289959","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289959","url":null,"abstract":"Proves a property of the second lowest weight spanning tree with color constraint. It enables one to enumerate color-constrained spanning trees in the increasing order of their weights by generalizing existing algorithms for the uncolored problem. A version of the algorithm is implemented in a program for the approximate symbolic analysis of large analog circuits.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132422102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures 估计矩形和l形角拼接数据结构的存储需求
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289999
D. Mehta
{"title":"Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures","authors":"D. Mehta","doi":"10.1109/GLSV.1994.289999","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289999","url":null,"abstract":"This paper proposes a technique for estimating the storage requirements of the Rectangular Corner Stitching (RCS) data structure and the L-Shaped Corner Stitching (LCS) date structure on a given circuit by studying its (the circuit's) geometric properties. This provides a method for estimating the storage requirements of a circuit without having to implement the Corner Stitching data structure, which is a tedious and time-consuming task. This technique can also be used to estimate the amount of space saved by employing the LCS data structure over the RCS data structure on a given circuit.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130895304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ADD-based algorithm for shortest path back-tracing of large graphs 基于add的大型图的最短路径回溯算法
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289960
R. I. Bahar, G. Hachtel, Abelardo Pardo, M. Poncino, F. Somenzi
{"title":"An ADD-based algorithm for shortest path back-tracing of large graphs","authors":"R. I. Bahar, G. Hachtel, Abelardo Pardo, M. Poncino, F. Somenzi","doi":"10.1109/GLSV.1994.289960","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289960","url":null,"abstract":"Symbolic computation techniques play a fundamental role in logic synthesis and formal hardware verification algorithms. Recently, Algebraic Decision Diagrams, i.e., BDDs with a set of constant values different to the set /spl lcub/0,1/spl rcub/, have been used to solve general purpose problems, such as matrix multiplication, shortest path calculation, and solution of linear systems, as well as logic synthesis and formal verification problems, such as timing analysis, probabilistic analysis of finite state machines, and state space decomposition for approximate finite state machine traversal. ADD-based procedures for single-source and all-pairs shortest path weight calculation have appeared to be very effective for the manipulation of large graphs (over 10/sup 27/ vertices and 10/sup 36/ edges). However, for those procedures to be applicable to real problems, for example flow network problems, computing only shortest path weights is not enough; what it is needed is an algorithm that, given the weight of a shortest path between two vertices of a graph, actually determines the sequence of vertices belonging to the shortest path. This paper proposes a symbolic algorithm to execute shortest path back-tracing which exploits the compactness of the ADD data structure to handle large graphs.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115546795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Routability crossing distribution and floating terminal assignment of T-type junction region t型结区的可达性交叉分布与浮动终端分配
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289976
Jin-Tai Yan, P.-Y. Hsiao
{"title":"Routability crossing distribution and floating terminal assignment of T-type junction region","authors":"Jin-Tai Yan, P.-Y. Hsiao","doi":"10.1109/GLSV.1994.289976","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289976","url":null,"abstract":"In this paper, two routability crossing distribution problems based on the non-crossing relations, vertical constraint relations and geometry relations are proposed to improve routing performance of one T-type junction region. For the routability problem, a routability ordering graph can be built to decide a net ordering on the boundary in O(n/sup 2/) time. Furthermore, for the routability quota problem, if the number of crossings for the routability problem is more than the quota, the net ordering in the routability problem must be adjusted by a net interchange operation to satisfy the quota requirement in the routability quota problem in O(n) time. Since a net ordering is obtained in the routability problem or the routability quota problem, the global nets will be assigned onto the boundary in O(n) time by interleaving vacant terminals between any pair of global nets for the floating terminal assignment of the boundary.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"175 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120893129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A distributed controller for system level integration 用于系统级集成的分布式控制器
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290006
M. Vashi, V. K. Raj, H. Youn
{"title":"A distributed controller for system level integration","authors":"M. Vashi, V. K. Raj, H. Youn","doi":"10.1109/GLSV.1994.290006","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290006","url":null,"abstract":"Currently large digital systems consist of a control unit and many processing units. Much work has been done in partitioning large processing units (PUs) into multiple PUs. However, there is still a large control unit that must control each of these PUs. This results in long lines from the control unit to the PUs and hence a long clock period. We present a method to break the control unit into many smaller control units (local CUs) so that each of these local CUs can sit on the same chip as the PU that it controls. These local CUs are partitioned in such a fashion that there is a pipelined sequence of execution between them.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121745787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling of serially-connected MOSFET chains 串联MOSFET链的缩放
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289969
S. Vemuru
{"title":"Scaling of serially-connected MOSFET chains","authors":"S. Vemuru","doi":"10.1109/GLSV.1994.289969","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289969","url":null,"abstract":"Scaling of serially-connected MOSFETs results in reduced propagation delays and power dissipation. Delay formulae and optimum scaling factors are derived as functions of capacitive load, diffusion capacitance and number of MOSFETs in the serially-connected chain using exponential-scaling and linear-scaling methods.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134621068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Wiring pitch integrates MCM design domains 布线间距集成了MCM设计领域
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289983
James Loy, A. Garg, M. Krishnamoorthy, J. McDonald
{"title":"Wiring pitch integrates MCM design domains","authors":"James Loy, A. Garg, M. Krishnamoorthy, J. McDonald","doi":"10.1109/GLSV.1994.289983","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289983","url":null,"abstract":"MCM designs require independent analysis in loosely coupled but interrelated design regimes. This paper proposes wiring pitch as the unifying thread in a real time iterative design environment that facilitates analysis in all pertinent domains. Actual system results demonstrate the strengths of the technique.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI implementation of CORDIC angle units CORDIC角度单位的VLSI实现
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289979
Jeong-A Lee, Mubashir Ahmad
{"title":"VLSI implementation of CORDIC angle units","authors":"Jeong-A Lee, Mubashir Ahmad","doi":"10.1109/GLSV.1994.289979","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289979","url":null,"abstract":"We design angle units using Lager tools both by a conventional CORDIC algorithm and a fast algorithm called Constant-Factor Redundant CORDIC (CFR-CORDIC) and show that the CFR-CORDIC occupies more than twice the area of a conventional CORDIC but offers good speed-up. We discuss VLSI design issues using Lager such as system partitioning and grouping, floor planning, width and height manipulation to obtain the smallest geometry, and the limitation of the standard cell design approach. In addition, a bit encoding scheme of a signed digit number representation, which simplifies the implementation of the negation is presented.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient algorithm for the realizability analysis of signal transition graphs 一种有效的信号转换图可实现性分析算法
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289974
H. F. Li, S. Leung
{"title":"An efficient algorithm for the realizability analysis of signal transition graphs","authors":"H. F. Li, S. Leung","doi":"10.1109/GLSV.1994.289974","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289974","url":null,"abstract":"This paper presents a necessary and sufficient condition for realizability from signal transition graphs to circuits that use the complex gate implementation method. A polynomial time algorithm is developed for checking the condition. The advantages of performing checking in signal transition graphs lie in its avoiding state space enumeration and searching, which incur exponential complexity due to concurrency.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122840803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing cyclic data-flow graphs via associativity 利用结合律优化循环数据流图
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290005
L. Chao
{"title":"Optimizing cyclic data-flow graphs via associativity","authors":"L. Chao","doi":"10.1109/GLSV.1994.290005","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290005","url":null,"abstract":"An iterative or recursive algorithm, with interiteration precedence relations is represented by a cyclic data-flow graph (DFG), where nodes represented operations. Such a DFG has a lower bound on the schedule length, which is determined by the loops (cycles) in the cyclic DFG. Associativity of the operations can be applied to restructure a DFC while preserving the behavior of the given recursive algorithm. We propose a measure of criticalness on regions of a DFG in order to guide the application of associativity to effectively reduce the lower bound or schedule length. Experimental results show that the transformed dataflow graph gives the best known schedules even under resource constraints.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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