{"title":"一种有效的信号转换图可实现性分析算法","authors":"H. F. Li, S. Leung","doi":"10.1109/GLSV.1994.289974","DOIUrl":null,"url":null,"abstract":"This paper presents a necessary and sufficient condition for realizability from signal transition graphs to circuits that use the complex gate implementation method. A polynomial time algorithm is developed for checking the condition. The advantages of performing checking in signal transition graphs lie in its avoiding state space enumeration and searching, which incur exponential complexity due to concurrency.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An efficient algorithm for the realizability analysis of signal transition graphs\",\"authors\":\"H. F. Li, S. Leung\",\"doi\":\"10.1109/GLSV.1994.289974\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a necessary and sufficient condition for realizability from signal transition graphs to circuits that use the complex gate implementation method. A polynomial time algorithm is developed for checking the condition. The advantages of performing checking in signal transition graphs lie in its avoiding state space enumeration and searching, which incur exponential complexity due to concurrency.<<ETX>>\",\"PeriodicalId\":330584,\"journal\":{\"name\":\"Proceedings of 4th Great Lakes Symposium on VLSI\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-03-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1994.289974\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1994.289974","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient algorithm for the realizability analysis of signal transition graphs
This paper presents a necessary and sufficient condition for realizability from signal transition graphs to circuits that use the complex gate implementation method. A polynomial time algorithm is developed for checking the condition. The advantages of performing checking in signal transition graphs lie in its avoiding state space enumeration and searching, which incur exponential complexity due to concurrency.<>