{"title":"An efficient multiprocessor implementation scheme for real-time DSP algorithms","authors":"Y. Hu, Duen-Jeng Wang","doi":"10.1109/GLSV.1994.289971","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289971","url":null,"abstract":"An algorithm to derive minimum-processor implementation for real-time DSP algorithms is proposed. In order to make the number of possible schedules finite and to assure the optimal schedule within the search space, the authors define a novel notion of cutoff time. All the possible schedules can find an equivalent schedule that finishes before cutoff time. Next, they apply all efficient heuristic periodic scheduling and fully static allocation algorithms derived from two generic problem solving heuristics developed in a branch of artificial intelligence research called planning. Extensive benchmarks have been tested and the results are most encouraging.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121095514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yulin Chen, W. Tsai, F. Kurdahi, T. Her, C. Ramachandran
{"title":"A performance driven logic synthesis system using delay estimator","authors":"Yulin Chen, W. Tsai, F. Kurdahi, T. Her, C. Ramachandran","doi":"10.1109/GLSV.1994.289990","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289990","url":null,"abstract":"In this paper, we develop a logic synthesis approach which relies on accurate design evaluation program to estimate the final design attributes such as layout speed. Given a candidate design implementation, an evaluation program is called upon to provide quick and accurate estimates of the critical path delay. This information is then used as a feedback to the logic optimization system. Based on this feedback, the system will \"re-orient\" itself toward a new direction for optimization. Such a scheme represents a more realistic way of generating optimal layout implementations.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An energy-efficient CMOS line driver using adiabatic switching","authors":"W. Athas, J. Koller, L. Svensson","doi":"10.1109/GLSV.1994.289970","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289970","url":null,"abstract":"Describes a custom CMOS line driver chip and a resonant power supply that can switch eight 100 pF loads at 1 MHz six times more efficiently than a conventional (CV/sup 2/) CMOS solution. The authors describe the adiabatic charging principle used, which allows a digital circuit designer to directly trade off switching time for increased energy efficiency. Emphasis is placed on evaluating the dissipation overhead for the whole system including the power supply. Measurements confirm the predicted dissipation decrease.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122523539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A gridless multi-layer area router","authors":"Naresh Sehgal, C. Y. Chen, J. Acken","doi":"10.1109/GLSV.1994.289977","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289977","url":null,"abstract":"This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114148855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Retiming algorithms with application to VLSI testability","authors":"D. Kagaris, S. Tragoudas","doi":"10.1109/GLSV.1994.289966","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289966","url":null,"abstract":"A very popular and established methodology for testing complex sequential circuits is to break the cyclic structure of the circuit by incorporating a minimum number of flip-flops into a partial scan register. The circuit can then be tested by applying sequences of test patterns or using techniques for testing combinational logic. In the former case, it is very important to minimize the sequential depth, i.e. the maximum number of flip-flops on any path from the inputs to the outputs. In the latter case, it is also necessary to balance the circuit, so that all paths between any pair of nodes have the same number of flip-flops. In this paper, we address the above goals using the sequential logic synthesis concept of retiming. We present polynomial-time algorithms that solve optimally the following problems: (i) minimization of the sequential depth of the circuit; (ii) minimization of the number of flip-flops in the circuit so that the sequential depth and the clock period are less than prescribed bounds; and (iii) minimization of the number of flip-flops that need to be inserted in the circuit so that it becomes balanced. These algorithms extend the areas where retiming can be successfully applied.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121963840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Distributed data-path synthesis on a network of workstations","authors":"M. E. Dalkiliç, V. Pitchumani","doi":"10.1109/GLSV.1994.289973","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289973","url":null,"abstract":"Presents a distributed data-path synthesis approach which taps into the vast and cheap computing power of the distributed computing environments. The synthesis program is based on a novel approach where all processors simultaneously generate optimal schedules and allocate data-paths for them using a simple but powerful set of binding algorithms. The experimental results show that the distributed synthesis approach is very effective for exploring the design space.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133328597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mathematical model for routability analysis of FPGAs","authors":"D. Bhatia, Amit Chowdhary, S. Tragoudas","doi":"10.1109/GLSV.1994.289992","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289992","url":null,"abstract":"We have developed a mathematical model for estimating the probability of routing on an electrically programmable logic cell array (LGA). Using the model the variation of the routability or the probability of routing with the average span of the nets, and flexibility of programming resources is determined. The results obtained from the model have been verified experimentally. As expected, the routability also increases when the number of programming elements is increased. We also show a three dimensional relationship between routability, placement, and programming flexibility. Our results show a strong relationship between module placement and the routability for an LCA.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"88 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130770249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated system partitioning for synthesis of multi-chip modules","authors":"R. V. Cherabuddi, M. Bayoumi","doi":"10.1109/GLSV.1994.290003","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290003","url":null,"abstract":"We present a system-level partitioning technique for the synthesis of multi-chip modules. It is based on the stochastic evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. We perform the partitioning at the behavioral level. The advantage of partitioning at the behavioral level is that both area and time constraints can be taken care of at the system level and also that scheduling/allocation can be applied concurrently to system-level partitioning. We formulate the partitioning problem as an extension to the network-bisectioning problem for which the stochastic evolution heuristic has been shown to provide better results than the simulated annealing technique. Preliminary scheduling/allocation and pin sharing are also performed simultaneously to estimate the area and pincount of each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130304546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a 54-bit adder using a modified Manchester carry chain","authors":"R. Hashemian","doi":"10.1109/GLSV.1994.289968","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289968","url":null,"abstract":"A new design based on a modified Manchester carry adder is presented. The modification provides bypass routes for the carry to propagate when the carry path through the chain is long. The computational speed received is quite high for high density codes. Much similar to carry look-ahead adders the bypass routes are activated through a series of group carries, in different levels, generated by a NAND/NOR tree network. It is shown that for a 54-bit adder the longest delay through the carry chain is equivalent to the delay through only 11 pass transistors. The algorithm is implemented for the design of a 54-bit adder using CMOS technology.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133548522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of transport triggered architectures","authors":"H. Corporaal","doi":"10.1109/GLSV.1994.289981","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289981","url":null,"abstract":"Transport triggered architectures (TTAs) form a superclass of traditional very large instruction word (VLIW) architectures, in the sense that they not only exploit operation style parallelism, but also the parallelism available at data transport level. This is possible by making all transports visible to the compiler. The main advantages of transport triggered architectures are simplicity and flexibility, allowing short processor cycle times and a quick (application specific) processor design. Transport triggered architectures also have certain advantages with respect to scheduling freedom and transport utilization. The paper discusses the concept of transport triggering and its corresponding advantages. It further concentrates on a prototype VLSI implementation in a 1.6 /spl mu/ Sea of Gates technology, called MOVE32INT, which demonstrates the feasibility of transport triggering. Finally it explores the automatic generation of arbitrary TTAs.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127680901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}