Design of a 54-bit adder using a modified Manchester carry chain

Abstract

A new design based on a modified Manchester carry adder is presented. The modification provides bypass routes for the carry to propagate when the carry path through the chain is long. The computational speed received is quite high for high density codes. Much similar to carry look-ahead adders the bypass routes are activated through a series of group carries, in different levels, generated by a NAND/NOR tree network. It is shown that for a 54-bit adder the longest delay through the carry chain is equivalent to the delay through only 11 pass transistors. The algorithm is implemented for the design of a 54-bit adder using CMOS technology.<>