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Proceedings of 4th Great Lakes Symposium on VLSI最新文献

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A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks 多处理机互连网络中基于VLSI cam的柔性无关路由器
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289982
J. Delgado-Frías, Rovy Sze, D. Summerville, V. C. Aikens
{"title":"A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks","authors":"J. Delgado-Frías, Rovy Sze, D. Summerville, V. C. Aikens","doi":"10.1109/GLSV.1994.289982","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289982","url":null,"abstract":"A VLSI implementation of a flexible router scheme for parallel interconnection network architectures is presented in this paper. The router implements implicit oblivious routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. To further increase performance, the router operation has been made pipelined with a throughput of 1 routing decision per cycle. The implementation is based on a combination of a content addressable memory that supports per entry unique bit masking, a fast priority scheme that allows only one entry to be selected, and a memory that stores the port assignment. The number of required CAM entries is extremely small; it is of the same order as the output ports (or node degree).<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114845401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Area, performance, and sensitizable paths /spl lsqb/logic design/spl rsqb/ 面积、性能和敏感路径/spl lsqb/逻辑设计/spl rsqb/
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289965
B. Kapoor, S. Nair
{"title":"Area, performance, and sensitizable paths /spl lsqb/logic design/spl rsqb/","authors":"B. Kapoor, S. Nair","doi":"10.1109/GLSV.1994.289965","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289965","url":null,"abstract":"In this paper, we investigate the problem of modifying a synthesized circuit to improve its path sensitizability. It is shown that a large number of paths, which cannot be sensitized using single-transition tests, are redundant paths and they can be removed by appropriate modification of the circuit. The effect of these modifications on area and performance of the circuit has been analyzed. For the paths which are neither redundant nor sensitizable using single-transition tests, it is shown that they can be sensitized using multiple-transition tests. Results obtained on some common benchmark examples suggest the validity and viability of this approach.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"587 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132719937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a package for a high-speed processor made with yield-limited technology 用产量有限的技术制造高速处理器的封装设计
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289985
A. Garg, James Loy, H. Greub, J. McDonald
{"title":"Design of a package for a high-speed processor made with yield-limited technology","authors":"A. Garg, James Loy, H. Greub, J. McDonald","doi":"10.1109/GLSV.1994.289985","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289985","url":null,"abstract":"The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131088392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Floorplanning for mixed macro block and standard cell designs 混合宏块和标准单元设计的平面规划
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290001
A. Shanbhag, Srinivasa R. Danda, N. Sherwani
{"title":"Floorplanning for mixed macro block and standard cell designs","authors":"A. Shanbhag, Srinivasa R. Danda, N. Sherwani","doi":"10.1109/GLSV.1994.290001","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290001","url":null,"abstract":"In this paper, we present ARCHITECT, the floorplanner for high performance Mixed Block and Cell designs. A novel and significant feature of ARCHITECT is that it exploits the flexibility of the standard cell regions by generating arbitrary rectilinear shapes for the flexible blocks. We have implemented ARCHITECT on a Sun SPARC station 1+ using C and Xview. We have tested the floorplanner on various randomly generated examples. Experimental results indicate that ARCHITECT generates floorplans with minimal white space within the user specified bounds.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"58 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors FFT处理器使用并发错误检测的基于算法的容错(多于一个错误)
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289995
Chin-Chicn Sha, Robcrt W. Lcavcnc
{"title":"An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors","authors":"Chin-Chicn Sha, Robcrt W. Lcavcnc","doi":"10.1109/GLSV.1994.289995","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289995","url":null,"abstract":"An algorithm is proposed to maintain fault tolerance for a highly reliable FFT processor, even after the processor has been reconfigured (by detecting a single fault). It proves that the concurrent error detection (CED) scheme using: a redundant stage of decimation in frequency FFT (DIF-FFT) butterflies as a decoder can detect all the faults theoretically. This CED scheme and the modification of the standard DIF-FFT processor as a recirculated shuffle exchange will also alleviate the difficulty of reconfiguration and will provide the ability of some degradation in performance in the presence of more than one fault in the processor.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125112090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An optimal algorithm for maximum two planar subset problem /spl lsqb/VLSI layout/spl rsqb/ 最大两个平面子集问题的最优算法/spl lsqb/VLSI布局/spl rsqb/
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289991
A. Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, N. Sherwani
{"title":"An optimal algorithm for maximum two planar subset problem /spl lsqb/VLSI layout/spl rsqb/","authors":"A. Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, N. Sherwani","doi":"10.1109/GLSV.1994.289991","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289991","url":null,"abstract":"The Two Row Maximum Planar Subset (TRMPS) problem asks for finding the maximum planar subset of nets, that can be routed between two rows of terminals an a cell row. This problem was first encountered by Gong, Liu, and Preas (1990). They declared it open, and presented an approximation algorithm for this problem. In this paper we show that TRMPS problem can be solved optimally in polynomial time, and we present an O(kn/sup 2/) algorithm to solve this problem. Our algorithm can also be extended to solve the TRMPS problem, in the presence of pre-routed nets, a chosen subset of nets, as well as for planar channel routing. We also apply our technique to obtain an improved approximation algorithm, for over the cell routing in middle terminal model standard cell layouts.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Basic building blocks for asynchronous packet routers 异步分组路由器的基本构建块
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289972
I. Nedelchev, C. Jesshope
{"title":"Basic building blocks for asynchronous packet routers","authors":"I. Nedelchev, C. Jesshope","doi":"10.1109/GLSV.1994.289972","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289972","url":null,"abstract":"Propagating the clock through large networks and providing correct functioning of the system is a serious engineering problem. The clock appears at different moments for two different physical points/spl minus/clock skew problem. While the clock skew can be neglected for small systems, it results in major problems when building large concurrent networks. To overcome such problems the authors believe that the absolute solution is to eliminate the notion of clocking entirely throughout by adopting asynchronous design techniques. Packet switches are familiar components of concurrent architectures and a good example to illustrate asynchronous design. The paper describes the asynchronous implementation of three basic building blocks for asynchronous packet routers and also demonstrates asynchronous design techniques for VLSI design.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On computational complexity of a detailed routing problem in two dimensional FPGAs 二维fpga中详细路由问题的计算复杂度
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289993
Yu-Liang Wu, S. Tsukiyama, M. Marek-Sadowska
{"title":"On computational complexity of a detailed routing problem in two dimensional FPGAs","authors":"Yu-Liang Wu, S. Tsukiyama, M. Marek-Sadowska","doi":"10.1109/GLSV.1994.289993","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289993","url":null,"abstract":"In this paper, we consider the problem of mapping a given global route to a detailed route for two dimensional homogeneous FPGAs. It has been shown that this problem is NP-complete on a popular Xilinx-4000-like routing architecture. Here, we further prove that this problem remains NP-complete for an arbitrary fixed switch box topology of the same connection flexibility, with or without doglegs allowed in detailed routes.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
ASIC design for robust signal and image processing ASIC设计用于鲁棒信号和图像处理
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289980
R. Schultz, H. M. Zeyedt, R. Stevenson, R. Minniti, C. H. Bernstein
{"title":"ASIC design for robust signal and image processing","authors":"R. Schultz, H. M. Zeyedt, R. Stevenson, R. Minniti, C. H. Bernstein","doi":"10.1109/GLSV.1994.289980","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289980","url":null,"abstract":"Maximum a posteriori (MAP) estimation using a robust signal model is capable of extracting a signal from additive noise, preserving edges in the signal estimate. A digital network can compute the estimate numerically using the gradient descent algorithm, or an analog network can be designed which provides the estimate as a steady-state output. An ASIC designed to perform robust signal processing has been manufactured, using the Huber-Markov random field (HMRF) signal model. This robust model is dependent upon two tunable parameters, which may be adjusted for a particular signal due to the design of novel analog circuit blocks.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129255699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Structural fault tolerance in VLSI-based systems vlsi系统的结构容错
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289996
Hung-Kuei Ku, J. Hayes
{"title":"Structural fault tolerance in VLSI-based systems","authors":"Hung-Kuei Ku, J. Hayes","doi":"10.1109/GLSV.1994.289996","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289996","url":null,"abstract":"A system is structurally fault-tolerant (SFT) if it preserves a fault-free subsystem of a pre-determined interconnection structure when faults appear. We present a systematic approach to designing SFT VLSI-based systems that use shared buses as the main communication mechanism. To represent the target systems, we introduce a processor-bus-link (PBL) graph in which processing elements (PEs) and buses are both modeled as nodes. PE and bus faults correspond to the removal of nodes from the PBL graph. The node covering concept and the minimum-weight spanning arborescence algorithm are then applied to the design of SFT systems that can tolerate both PE and bus faults. The designs obtained have fewer spare communication ports than prior designs, no critical single point of failure, and simple circuitry for reconfiguration.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"10 2A 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115341953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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