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Proceedings of 4th Great Lakes Symposium on VLSI最新文献

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Generalized segmented channel routing 通用分段信道路由
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289994
V. Shankar, D. Bhatia
{"title":"Generalized segmented channel routing","authors":"V. Shankar, D. Bhatia","doi":"10.1109/GLSV.1994.289994","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289994","url":null,"abstract":"This paper presents the first efficient solution to the generalized detailed routing problem in segmented channels for row-based FPGAs. A generalized detailed routing allows routing of each connection using an arbitrary number of tracks, i.e. doglegs are allowed. This approach is different from the normally followed method where each connection is routed on a single straight track. We present a router that performs generalized segmented channel routing using a greedy approach to route channels. It uses effective data-structures and pruning heuristics to keep down the time and memory requirements of the router.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115443198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A flow based approach to the pin redistribution problem for multi-chip modules 基于流的多芯片模块引脚重分配问题的研究
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289984
D. Chang, T. Gonzalez, O. Ibarra
{"title":"A flow based approach to the pin redistribution problem for multi-chip modules","authors":"D. Chang, T. Gonzalez, O. Ibarra","doi":"10.1109/GLSV.1994.289984","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289984","url":null,"abstract":"Investigates the pin redistribution problem (PRP) for multi-chip modules. A novel transformation to the max-flow problem is introduced. This approach provides an efficient algorithm for finding a 2-layer solution, whenever one exists. A greedy heuristic to find a k-layer solution is described. The approach can find a minimum layer solution for two variants of the PRP; when each net can be routed on more than one layer, and when source and target terminals are drilled through all layers. Except for the heuristic procedure which takes O(km/sup 4/ log/sup 2/ m) time, the algorithms take O(/spl verbar/S/spl verbar/km/sup 2/) time, where S is the set of source terminals, m is the number of rows and columns in the grid, and k is the number of layers required. One can show that generalizations of the k-layer PRP are NP-complete problems.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126226397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An improved algorithm for the generalized min-cut partitioning problem 广义最小分割问题的一种改进算法
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289961
S. Tragoudas
{"title":"An improved algorithm for the generalized min-cut partitioning problem","authors":"S. Tragoudas","doi":"10.1109/GLSV.1994.289961","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289961","url":null,"abstract":"We consider the generalization of the min-cut partitioning problem in which the nodes of a circuit C are to be mapped to the vertices of a graph G, and the cost function to be minimized is the cost of associating the nets of C with the edges of G. Vijayan (see IEEE Trans. on Computers, vol. 40, no. 3, 1991) recently presented an iterative improvement heuristic for the case when G is a tree T. Let P be the number of pins, t be the number of nodes of T, and d be the maximum number of cells on a net of C. The running time of a pass of the heuristic given in Vijayan's paper is O(P/spl middot/t/sup 3/). For a graph G, this approach requires O(P/spl middot/t/sup 4/) time per pass. We present a heuristic for this particular problem which guarantees exactly the same partitions in time O(P/spl middot/t min/spl lcub/d,t/spl rcub/) per pass, for any graph G. The problem finds important applications in a variety of situations that arise in VLSI physical design, and in distributed systems.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Communication based multilevel synthesis for multi-output Boolean functions 基于通信的多输出布尔函数多级综合
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289987
P. Molitor, Christoph Scholl
{"title":"Communication based multilevel synthesis for multi-output Boolean functions","authors":"P. Molitor, Christoph Scholl","doi":"10.1109/GLSV.1994.289987","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289987","url":null,"abstract":"A multilevel logic synthesis technique for multi-output Boolean functions is presented which is based on minimizing the communication complexity. Unlike previous approaches, which in the final analysis decompose each single-output function f/sub i/ of a multi-output function f=(f/sub 1/, ..., f/sub m/) independently of the other single-output functions f/sub j/ (j/spl ne/i), the approach presented in this paper gives special attention to the fact that there possibly exist some decomposition functions which can be used by different outputs during the decomposition of the single-output functions of f. The benchmarking results (taken from 1991 MCNC multilevel logic benchmarks) which close the paper are promising.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115280680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Abstraction of data path registers for multilevel verification of large circuits 大型电路多级验证中数据路径寄存器的抽象
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290004
Y. Hoskote, J. Moondanos, J. Abraham, D. Fussell
{"title":"Abstraction of data path registers for multilevel verification of large circuits","authors":"Y. Hoskote, J. Moondanos, J. Abraham, D. Fussell","doi":"10.1109/GLSV.1994.290004","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290004","url":null,"abstract":"Automatic verification of implementations against their specifications in the design hierarchy is largely based on state machine comparison. This paper presents a simple technique that exploits information about correspondence between registers in the data path to enable abstraction of data path registers and make automatic verification of circuits with large date paths tractable. Correspondence between registers which encode the control states is not required. This generality enables efficient verification of large circuits with data paths structured differently, as well as verification against specifications devoid of structural information. Results are presented for the verification of realistic circuits at different levels in the design hierarchy.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114794331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Floorplan area optimization using genetic algorithms 利用遗传算法优化楼面面积
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.290002
M. Rebaudengo, M. Reorda
{"title":"Floorplan area optimization using genetic algorithms","authors":"M. Rebaudengo, M. Reorda","doi":"10.1109/GLSV.1994.290002","DOIUrl":"https://doi.org/10.1109/GLSV.1994.290002","url":null,"abstract":"The paper deals with the problem of Floorplan Area Optimization; an approach based on Genetic Algorithms is proposed. The method produces optimal results with CPU time requirements comparable with the ones of other approaches but presents some advantages: it is simple to implement, it allows the user to easily trade off CPU time with result accuracy, it requires a limited amount of memory to store partial results, it is not sensible to special structures like nested wheels. Experimental results on the biggest problems proposed in the literature are reported.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132562080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new scheme to compute variable orders for binary decision diagrams 一种计算二元决策图变量阶数的新方案
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289986
J. Jain, J. Bitner, Dinos Moundanos, J. Abraham, D. Fussell
{"title":"A new scheme to compute variable orders for binary decision diagrams","authors":"J. Jain, J. Bitner, Dinos Moundanos, J. Abraham, D. Fussell","doi":"10.1109/GLSV.1994.289986","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289986","url":null,"abstract":"Introduces some new methods for estimating the \"importance\" of a variable in a Boolean function, and uses them to compute variable orders for OBDD construction. These measures are based on information theoretic criteria, and require the computation of the entropy of a variable in a given function. These entropy measures prove quite effective in distinguishing the importance of variables. Experimental results show this to be a very encouraging approach to help in the solution of this well known problem.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131860776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees 精确线性斯坦纳最小树的快速动态规划算法
Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI: 10.1109/GLSV.1994.289962
J. L. Ganley, J. Cohoon
{"title":"A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees","authors":"J. L. Ganley, J. Cohoon","doi":"10.1109/GLSV.1994.289962","DOIUrl":"https://doi.org/10.1109/GLSV.1994.289962","url":null,"abstract":"An exact rectilinear Steiner minimal tree algorithm is presented that improves upon the time and space complexity of previous guarantees and is easy to implement. Experimental evidence is presented that demonstrates that the algorithm also works well in practice.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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