A performance driven logic synthesis system using delay estimator

Abstract

In this paper, we develop a logic synthesis approach which relies on accurate design evaluation program to estimate the final design attributes such as layout speed. Given a candidate design implementation, an evaluation program is called upon to provide quick and accurate estimates of the critical path delay. This information is then used as a feedback to the logic optimization system. Based on this feedback, the system will "re-orient" itself toward a new direction for optimization. Such a scheme represents a more realistic way of generating optimal layout implementations.<>