Design of transport triggered architectures

Abstract

Transport triggered architectures (TTAs) form a superclass of traditional very large instruction word (VLIW) architectures, in the sense that they not only exploit operation style parallelism, but also the parallelism available at data transport level. This is possible by making all transports visible to the compiler. The main advantages of transport triggered architectures are simplicity and flexibility, allowing short processor cycle times and a quick (application specific) processor design. Transport triggered architectures also have certain advantages with respect to scheduling freedom and transport utilization. The paper discusses the concept of transport triggering and its corresponding advantages. It further concentrates on a prototype VLSI implementation in a 1.6 /spl mu/ Sea of Gates technology, called MOVE32INT, which demonstrates the feasibility of transport triggering. Finally it explores the automatic generation of arbitrary TTAs.<>