基于模拟退火的版图良率提高

Proceedings of 4th Great Lakes Symposium on VLSI Pub Date : 1994-03-04 DOI:10.1109/GLSV.1994.289975

R. Karri, A. Orailoglu

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引用次数: 0

摘要

本文提出了一种用于合成容缺陷布局的系统DEFT，该系统对制造过程中产生的缺陷具有晶内容限。这是通过将有大量重叠的网分散到不相邻的轨道上来实现的。DEFT还提供了面积(以轨道数量衡量)和结果布局的产量之间的权衡。由DEFT合成的容错布局始终优于其他布局综合系统生成的容错布局。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Simulated annealing based yield enhancement of layouts

This paper presents DEFT, a system for synthesizing defect-tolerant layouts, that in-grains tolerance to fabrication induced defects. This is accomplished by dispersing nets with large overlaps into nonadjacent tracks. DEFT also affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by DEFT have been consistently superior to those generated by other layout synthesis systems.<>

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Proceedings of 4th Great Lakes Symposium on VLSI

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