The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications

Abstract

In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<>