Low-power differential CML and ECL BiCMOS circuit techniques

Abstract

The performance of the different two-level series-gated CML BiCMOS schemes has been studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, have shown an improvement of 42% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating an the low power regime (<1 mW). Moreover, the BJT-MOS frequency divider configuration exhibits a high input sensitivity throughout the frequency range of operation. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.<>