Efficient simulation of switch-level circuits in a hierarchical simulation environment

Switch-level simulation provides a good level of abstraction for simulating digital MOS circuits. For handling large circuits, it is often necessary to represent parts of the circuit by high-level software models, in order to speed up the simulation process. This paper, considers hierarchical switch-level circuits, and investigates the use of extracted functional models at different levels in the hierarchy to increase the efficiency of simulation. A comparative study, on some sample circuits, is used to determine the ideal size of a module that should be simulated using its functional model.<>