{"title":"设计了一种适用于线性收缩阵列DSP的容错GEQRNS处理单元","authors":"Jermy C. Smith, F. Taylor","doi":"10.1109/GLSV.1994.289997","DOIUrl":null,"url":null,"abstract":"In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<<ETX>>","PeriodicalId":330584,"journal":{"name":"Proceedings of 4th Great Lakes Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications\",\"authors\":\"Jermy C. Smith, F. Taylor\",\"doi\":\"10.1109/GLSV.1994.289997\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<<ETX>>\",\"PeriodicalId\":330584,\"journal\":{\"name\":\"Proceedings of 4th Great Lakes Symposium on VLSI\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-03-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1994.289997\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1994.289997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications
In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<>
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