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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)最新文献

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A 20 Gbps scalable load-balanced TDM switch with CODEC for high speed networking applications 20 Gbps可扩展的负载均衡TDM交换机，具有编解码器，适用于高速网络应用
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.4
C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng
{"title":"A 20 Gbps scalable load-balanced TDM switch with CODEC for high speed networking applications","authors":"C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng","doi":"10.1109/IWSOC.2005.4","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.4","url":null,"abstract":"For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N/spl times/N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8/spl times/8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8/spl times/8 or 64/spl times/64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8/spl times/8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64/spl times/64 switch. All implementation were based on the 0.18 /spl mu/m CMOS technology.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126660970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Orthogonalized communication architecture for MP-SoC with global bus 具有全局总线的MP-SoC正交化通信体系结构
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.89
Jin Lee, Sin-Chong Park
{"title":"Orthogonalized communication architecture for MP-SoC with global bus","authors":"Jin Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.89","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.89","url":null,"abstract":"In platform based SoC design, the computational part and communication part of the system are required to be orthogonalized. In this paper, we propose the fully orthogonalized communication architecture of multi-processor SoC (MP-SoC) which has a global bus architecture. In order to orthognalize communication and computation, we use the central arbiter which not only performs arbitration of transactions, but generates of transaction information. Each master has a transactor which translate the information from the central arbiter, so that the master doesn't need to synchronize with other processors. This paper also provides the transaction level modeling (TLM) methodology at timed functional (TF) level with SystemC 2.0.1 and master-slave library.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS quality factor enhanced parallel resonant LC-tank with independent Q and frequency tuning for RF integrated filters 一种用于射频集成滤波器的具有独立Q和频率调谐的CMOS质量因数增强并联谐振LC-tank
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.5
J. Nakaska, J. Haslett
{"title":"A CMOS quality factor enhanced parallel resonant LC-tank with independent Q and frequency tuning for RF integrated filters","authors":"J. Nakaska, J. Haslett","doi":"10.1109/IWSOC.2005.5","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.5","url":null,"abstract":"A new quality factor enhanced resonator core is presented and used to design a bandpass filter at 2.4GHz. The new Q-enhanced LC-tank has independent Q tuning capability, which substantially simplifies the automatic Q-tuning problem. In simulation, the unloaded Q-enhanced core consumes 7.05mA from a 1.8V supply in 0.18/spl mu/m CMOS and can be tuned from 2.1GHz to 3.5GHz using varactors. A brief discussion of the proposed automatic Q-tuning system is presented. The synthesized 2.45GHz filter has a bandwidth of 148MHz, 0dB insertion loss over a 10% tuning range, and a 1/sup st/ order compression point of -0.5dBm at 2.35GHz.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Digital RF processing techniques for SoC radios (invited) 用于 SoC 无线电的数字 RF 处理技术（特邀）
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.54
R. Staszewski, K. Muhammad, D. Leipold
{"title":"Digital RF processing techniques for SoC radios (invited)","authors":"R. Staszewski, K. Muhammad, D. Leipold","doi":"10.1109/IWSOC.2005.54","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.54","url":null,"abstract":"In this paper, we describe key digital RF processing techniques behind the first single-chip Bluetooth and GSM/EDGE radios realized in 130-nm and 90-nm digital CMOS process technologies, respectively. The local oscillator, transmitter and receiver are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processors. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally-controlled oscillator and a time-to-digital converter, respectively. The transmitter employs a polar architecture with all-digital phase/frequency and amplitude modulation paths. The phase/frequency modulation is based on the direct wideband frequency modulation capability of an all-digital phase-locked loop. The amplitude modulation path directly is built on a digitally-controlled power amplifier. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The discrete-time filtering at each signal processing stage is followed by successive decimation, such that great selectivity is achieved right at the mixer level.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126985117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs esd诱导的内部核心器件失效:片上系统(SOC)设计中的新失效模式
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.58
Y. Huh, P. Bendix, Kyungjin Min, Jau-Wen Chen, R. Narayan, L. Johnson, S. Voldman
{"title":"ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs","authors":"Y. Huh, P. Bendix, Kyungjin Min, Jau-Wen Chen, R. Narayan, L. Johnson, S. Voldman","doi":"10.1109/IWSOC.2005.58","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.58","url":null,"abstract":"With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115213032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High level extraction of SoC architectural information from generic C algorithmic descriptions 从通用C算法描述中高层次地提取SoC架构信息
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.71
M. Mattavelli, M. Ravasi
{"title":"High level extraction of SoC architectural information from generic C algorithmic descriptions","authors":"M. Mattavelli, M. Ravasi","doi":"10.1109/IWSOC.2005.71","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.71","url":null,"abstract":"The complexity of nowadays, algorithms in terms of number of lines of codes and cross-relations among processing algorithms that are activated by specific input signals, goes far beyond what the designer can reasonably grasp from the \"pencil and paper\" analysis of the (software) specifications. Moreover, depending on the implementation goal different measures and metrics are required at different steps of the implementation methodology or design flow of SoC. The process of extracting the desired measures needs to be supported by appropriate automatic tools, since code rewriting, at each design stage, may result resource consuming and error prone. This paper presents an integrated tool for automatic analysis capable of producing complexity results based on rich and customizable metrics. The tool is based on a C virtual machine that allows extracting from any C program execution the operations and data-flow information, according to the defined metrics. The tool capabilities include the simulation of virtual memory architectures.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130221660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm 采用一种新的晶体管尺寸算法，提高CMOS DCVSL栅极的性能并节约能源
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.57
N. Masoumi, M. Ahmadian, F. Raissi, M. Masoumi, Jahan B. Ghasemi
{"title":"Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm","authors":"N. Masoumi, M. Ahmadian, F. Raissi, M. Masoumi, Jahan B. Ghasemi","doi":"10.1109/IWSOC.2005.57","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.57","url":null,"abstract":"In this paper we describe an algorithm for transistor sizing in CMOS DCVSL (differential cascode voltage switch logic) digital circuits. Our proposed method has two different approaches with low computational burden, mathematical based and genetic algorithm based. Using our transistor sizing algorithm, we minimized the propagation delay of a DCVSL full-adder and a DCVSL XOR in 0.5 /spl mu/m CMOS technology. At first, the optimum sizes of these circuits were calculated to obtain the minimum propagation delay. Then the final transistor sizes were obtained by trading off speed, energy and area to meet a set of performance requirements.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128511580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Floating-gate devices, circuits, and systems 浮栅装置、电路和系统
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.65
P. Hasler
{"title":"Floating-gate devices, circuits, and systems","authors":"P. Hasler","doi":"10.1109/IWSOC.2005.65","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.65","url":null,"abstract":"This paper describes our programmable analog technology based around floating-gate transistors that allow for non-volatile storage as well as computation through the same device. We describe the basic concepts for floating-gate devices, capacitor-based circuits, and the basic charge modification mechanisms that makes this analog technology programmable. We describe the techniques to extend these techniques to program an nonhomogenious array of floating-gate devices.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128808827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A multilevel eigenvalue based circuit partitioning technique 基于多电平特征值的电路划分技术
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.17
B. Schiffner, Jianhua Li, L. Behjat
{"title":"A multilevel eigenvalue based circuit partitioning technique","authors":"B. Schiffner, Jianhua Li, L. Behjat","doi":"10.1109/IWSOC.2005.17","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.17","url":null,"abstract":"VLSI circuit partitioning is an important step in the physical design of integrated circuits. In VLSI partitioning, a circuit is partitioned into smaller relatively independent sub-circuits. In this paper we present an eigenvalue based multilevel partitioning algorithm. The proposed method uses a matrix reordering technique to produce a minimal bandwidth matrix, relying upon matrix sparsity. The reordering technique is applied to the connectivity matrix of a clustered circuit and the matrix connectivity information is obtained. This connectivity information is used to partition the circuit. The experimental results demonstrate the technique's effectiveness against flat partitioning algorithms.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128951029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Global lower bounds for the VLSI macrocell floorplanning problem using semidefinite optimization 用半定优化方法求解VLSI宏单元布局问题的全局下界
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.69
P. L. Takouda, M. Anjos, A. Vannelli
{"title":"Global lower bounds for the VLSI macrocell floorplanning problem using semidefinite optimization","authors":"P. L. Takouda, M. Anjos, A. Vannelli","doi":"10.1109/IWSOC.2005.69","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.69","url":null,"abstract":"We investigate the application of semidefinite programming (SDP) techniques to the VLSI macrocell floorplanning problem. We propose a mixed-integer SDP formulation of the problem which leads to new SDP relaxations. This approach has been implemented and we report global lower bounds for some MCNC benchmark macrocell problems.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125440206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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