Digital RF processing techniques for SoC radios (invited)

In this paper, we describe key digital RF processing techniques behind the first single-chip Bluetooth and GSM/EDGE radios realized in 130-nm and 90-nm digital CMOS process technologies, respectively. The local oscillator, transmitter and receiver are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processors. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally-controlled oscillator and a time-to-digital converter, respectively. The transmitter employs a polar architecture with all-digital phase/frequency and amplitude modulation paths. The phase/frequency modulation is based on the direct wideband frequency modulation capability of an all-digital phase-locked loop. The amplitude modulation path directly is built on a digitally-controlled power amplifier. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The discrete-time filtering at each signal processing stage is followed by successive decimation, such that great selectivity is achieved right at the mixer level.