Orthogonalized communication architecture for MP-SoC with global bus

Abstract

In platform based SoC design, the computational part and communication part of the system are required to be orthogonalized. In this paper, we propose the fully orthogonalized communication architecture of multi-processor SoC (MP-SoC) which has a global bus architecture. In order to orthognalize communication and computation, we use the central arbiter which not only performs arbitration of transactions, but generates of transaction information. Each master has a transactor which translate the information from the central arbiter, so that the master doesn't need to synchronize with other processors. This paper also provides the transaction level modeling (TLM) methodology at timed functional (TF) level with SystemC 2.0.1 and master-slave library.