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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)最新文献

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Novel voltage-controlled oscillator design by MOS-NDR devices and circuits 基于MOS-NDR器件和电路的新型压控振荡器设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.87
Dong-Shong Liang, K. Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su
{"title":"Novel voltage-controlled oscillator design by MOS-NDR devices and circuits","authors":"Dong-Shong Liang, K. Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su","doi":"10.1109/IWSOC.2005.87","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.87","url":null,"abstract":"This paper describes the design of a voltage-controlled oscillator (VCO) based on the negative differential resistance (NDR) devices. The NDR devices used in the work is fully composed by the metal-oxide-semiconductor field-effect-transistor (MOS) devices. This MOS-NDR device can exhibit the NDR characteristic in its current-voltage curve by suitably arranging MOS parameters. The VCO is constructed by three low-power MOS-NDR inverter. This novel VCO has a range of operation frequency from 151MHz to 268MHz. It consumes 24.5mW in its central frequency of 260MHz using a 2 V power supply. This VCO is fabricated by 0.35 /spl mu/m CMOS process and occupied an area of 120 /spl times/ 86 /spl mu/m/sup 2/.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications 用于高速背板数据通信的四分之一速率时钟定时决策反馈均衡
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.48
Miao Li, P. Noel, T. Kwasniewski, Shoujun Wang
{"title":"Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications","authors":"Miao Li, P. Noel, T. Kwasniewski, Shoujun Wang","doi":"10.1109/IWSOC.2005.48","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.48","url":null,"abstract":"Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-/spl mu/m CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34\" FR4 backplane.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"401 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121791800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fast full search equivalent encoding algorithm for image vector quantization based on the WHT and a LUT 基于WHT和LUT的图像矢量量化快速全搜索等效编码算法
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.7
C. Ryu, S. Ra
{"title":"A fast full search equivalent encoding algorithm for image vector quantization based on the WHT and a LUT","authors":"C. Ryu, S. Ra","doi":"10.1109/IWSOC.2005.7","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.7","url":null,"abstract":"The application of vector quantization has been constrained to a great deal since its encoding process is very heavy. This paper presents a fast encoding algorithm called the double feature-ordered partial codebook search (DFPS) algorithm for image vector quantization. The DFPS algorithm uses the Walsh-Hadamard transform (WHT) for energy compaction and a look-up table (LUT) for fast reference. The simulation results show that with elaborate preprocessing and memory cost within a feasible level, the proposed DFPS algorithm is faster than other existing search algorithms. Compared with the exhaustive full search (EFS) algorithm, the DFPS algorithm reduces the computational complexity by 97.0% to 97.8% for a codebook size of 256 while maintaining the same encoding quality as that of the EFS algorithm.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flash memories for SoC: an overview on system constraints and technology issues SoC闪存:系统约束和技术问题概述
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.64
L. Larcher, P. Pavan, A. Maurelli
{"title":"Flash memories for SoC: an overview on system constraints and technology issues","authors":"L. Larcher, P. Pavan, A. Maurelli","doi":"10.1109/IWSOC.2005.64","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.64","url":null,"abstract":"Flash memories are today one of the fundamental building blocks in modern electronic systems. Their performance (speed, consumption, alterability, nonvolatility) and the increasing importance of system reconfigurability push for flash memory integration in SoC. Unfortunately, flash integration introduces new issues both at system and at circuit/technology levels that need to be deeply investigated. From the system point of view, several aspects are involved in the choice of the flash memory type to be integrated in SoC: the most important ones, depending on the specific applications and requirements (cost, power consumption, reliability and performance requirements), are illustrated. Also circuit-technology issues specific to flash integration with high-speed logic are discussed in depth by analyzing the real case of an embedded 1-T NOR flash memory.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A software/hardware platform for rapid prototyping of video and multimedia designs 一个软件/硬件平台，用于视频和多媒体设计的快速原型设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.27
P. Schumacher, M. Mattavelli, A. Chirila-Rus, R. Turney
{"title":"A software/hardware platform for rapid prototyping of video and multimedia designs","authors":"P. Schumacher, M. Mattavelli, A. Chirila-Rus, R. Turney","doi":"10.1109/IWSOC.2005.27","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.27","url":null,"abstract":"Traditional design and test of complex multimedia systems involves a large number of test vectors and is a difficult and time-consuming task. The simulation times are prohibitively long on current desktop computers. Driving actual design scenarios and timing burst behavior which produce real-time effects is difficult to do with current simulation environments. This paper describes a rapid emulation framework for accessing multiple hardware IP blocks on an FPGA. This solution involves an abstraction of the FPGA platform by having a virtual socket layer that resides between the design and the test vehicles. A rapid prototyping platform is thus created, and its use with complex video and multimedia systems is described.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A methodology for HW/SW specification and simulation at multiple levels of abstraction 一种在多个抽象层次上进行硬件/软件规范和模拟的方法
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.16
A. Tsikhanovich, E. Aboulhamid, G. Bois
{"title":"A methodology for HW/SW specification and simulation at multiple levels of abstraction","authors":"A. Tsikhanovich, E. Aboulhamid, G. Bois","doi":"10.1109/IWSOC.2005.16","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.16","url":null,"abstract":"In this paper we propose a new specification and simulation modeling methodology that supports the application of transactional level modeling in the design cycle of hardware/software (HW/SW) systems allowing the exploration and validation of design alternatives at high levels of abstraction. The proposed methodology offers a possibility to unify functional and nonfunctional aspects of the system yielding to a holistic approach in specification modeling and simulation. We provide a general approach in system specification that separates three modeling aspects: a computational model, a language used for the functional specification and simulator semantics and implementation. This enables model reusability, design space exploration and specification relatively independent from HW/SW description languages.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of 12-bit 100-MHz current-steering DAC for SOC applications 设计用于SOC应用的12位100 mhz电流转向DAC
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.51
Chun-Yueh Huang, T. Hou, Chi-Chieh Chuang, Hung-Yu Wang
{"title":"Design of 12-bit 100-MHz current-steering DAC for SOC applications","authors":"Chun-Yueh Huang, T. Hou, Chi-Chieh Chuang, Hung-Yu Wang","doi":"10.1109/IWSOC.2005.51","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.51","url":null,"abstract":"In this paper, we propose a 12-bit 100-MHz current-steering digital-to-analog converter (DAC) for system-on-a-chip (SOC) applications. We adapt the segmented architecture to design this DAC to obtain better performances of INL, glitch energy, and monotonicity. The segmented architecture includes 7-MSBs which are decoded into 127 equally weighted current sources and 5-LSBs which are corresponding to binary-weighted current sources. Based on the TSMC 0.35/spl mu/m 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL < /spl plusmn/0.4LSB, DNL < /spl plusmn/0.25LSB, and settling time less than 9ns. The proposed converter's spurious free dynamic ranges (SFDRs) for are larger than 80 dB and 65 dB at an update rate (f/sub CLK/) 100MHz and its output frequencies are 1 MHz and 49 MHz, respectively. The power consumption is 47 mW at the maximum conversion rate.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.3GHz CMOS transimpedance preamplifier for optical communication 用于光通信的2.3GHz CMOS透阻前置放大器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.3
Yanjie Wang, K. Iniewski
{"title":"A 2.3GHz CMOS transimpedance preamplifier for optical communication","authors":"Yanjie Wang, K. Iniewski","doi":"10.1109/IWSOC.2005.3","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.3","url":null,"abstract":"A 2.3GHz transimpedance preamplifier designed in a TSMC 0.18/spl mu/m CMOS technology for optical communication is presented. A wide-swing cascode (WSC) topology provides high transimpedance gain, wide bandwidth, large output voltage swing, low input impedance and low power consumption. The SpectreS simulations show a transimpedance gain of 1.12K/spl Omega/ (61dB/spl Omega/), 3-dB bandwidth of 2.3GHz, low input impedance (<50/spl Omega/), dynamic range of 66dB, 650mV output voltage swing and 2.3mW power consumption with 1.5V voltage supply.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An acoustic echo canceller chip 一种回声消除芯片
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.36
M. Borhani, V. Sedghi
{"title":"An acoustic echo canceller chip","authors":"M. Borhani, V. Sedghi","doi":"10.1109/IWSOC.2005.36","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.36","url":null,"abstract":"This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): subband adaptive filtering (SAF) and partitioned block Hartley domain adaptive filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in system on chip (SOC) or system in package (SIP) technologies.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125224843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction 模2/sup n/-1加减的面积缩减方案
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.38
Shaoqiang Bi, W. Gross, Wei Wang, A. Al-Khalili, M. Swamy
{"title":"An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction","authors":"Shaoqiang Bi, W. Gross, Wei Wang, A. Al-Khalili, M. Swamy","doi":"10.1109/IWSOC.2005.38","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.38","url":null,"abstract":"In this paper, we present a versatile area-reduced scheme for modulo 2/sup n/-1 adders and subtracters using a MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134485121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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