用于高速背板数据通信的四分之一速率时钟定时决策反馈均衡

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI:10.1109/IWSOC.2005.48

Miao Li, P. Noel, T. Kwasniewski, Shoujun Wang

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引用次数: 2

摘要

决策反馈均衡(DFE)是高速背板数据通信中常用的一种对抗码间干扰(ISI)的技术。针对DFE电路设计中对时钟时序速度的要求，提出了四分之一频率的时钟时序设计。采用0.18-/spl mu/m CMOS技术实现的接收器在34”FR4背板上的运行速度为6.25Gb/s和8Gb/s。

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Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications

Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-/spl mu/m CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34" FR4 backplane.

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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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