An acoustic echo canceller chip

Abstract

This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): subband adaptive filtering (SAF) and partitioned block Hartley domain adaptive filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in system on chip (SOC) or system in package (SIP) technologies.