An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction

Abstract

In this paper, we present a versatile area-reduced scheme for modulo 2/sup n/-1 adders and subtracters using a MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.