C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng
{"title":"A 20 Gbps scalable load-balanced TDM switch with CODEC for high speed networking applications","authors":"C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng","doi":"10.1109/IWSOC.2005.4","DOIUrl":null,"url":null,"abstract":"For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N/spl times/N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8/spl times/8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8/spl times/8 or 64/spl times/64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8/spl times/8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64/spl times/64 switch. All implementation were based on the 0.18 /spl mu/m CMOS technology.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.4","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N/spl times/N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8/spl times/8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8/spl times/8 or 64/spl times/64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8/spl times/8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64/spl times/64 switch. All implementation were based on the 0.18 /spl mu/m CMOS technology.