Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm

In this paper we describe an algorithm for transistor sizing in CMOS DCVSL (differential cascode voltage switch logic) digital circuits. Our proposed method has two different approaches with low computational burden, mathematical based and genetic algorithm based. Using our transistor sizing algorithm, we minimized the propagation delay of a DCVSL full-adder and a DCVSL XOR in 0.5 /spl mu/m CMOS technology. At first, the optimum sizes of these circuits were calculated to obtain the minimum propagation delay. Then the final transistor sizes were obtained by trading off speed, energy and area to meet a set of performance requirements.