2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)最新文献_第2页

Fault-pattern oriented defect diagnosis for flash memory 面向故障模式的闪存缺陷诊断

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.13

Mu-Hsien Hsu, Yu-Tsao Hsing, J. Yeh, Cheng-Wen Wu

引用次数: 5

Dynamic data stability in SRAM cells and its implications on data stability tests SRAM单元的动态数据稳定性及其对数据稳定性测试的影响

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.12

M. Sharifkhani, S. Jahinuzzaman, M. Sachdev

引用次数: 8

Comparison of electrical and reliability characteristics of different tunnel oxides in SONOS flash memory SONOS快闪记忆体中不同隧道氧化物的电学特性及可靠性比较

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.8

Jia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shi-Hsien Chen, H. Hwang, S. Pittikoun, Travis Cho, C. Kao

引用次数: 6

Non-volatile Semiconductor Memory Technology in Nanotech Era 纳米技术时代的非易失性半导体存储技术

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.21

Chih-Yuan Lu

引用次数: 3

High-Quality Memory Test 高质量记忆测验

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.17

M. Azimane

{"title":"High-Quality Memory Test","authors":"M. Azimane","doi":"10.1109/MTDT.2006.17","DOIUrl":"https://doi.org/10.1109/MTDT.2006.17","url":null,"abstract":"Semiconductor Companies are continuously trying to keep their customers Happy and Satisfied with new products, new functionalities and new interfaces. To keep track on inventing products with new more facilities, Semiconductor Companies have to include much more transistors per millimeter square than ever before. Nowadays, System on Chips (SoCs) are very dense, approaching 1 billion of transistors per chip of few millimeters. Interaction of this huge number of transistors in a chip is becoming much more important than few years ago. To be specific, in current process technologies new defects mechanisms and process variation are causing complex faulty behaviours, which are creating new challenges for test experts. Moreover, embedded memories occupy a big portion of SoCs approaching nowadays 70% of total SoC area and are infringing the DFM rules, which creates even higher defect density than logic or analog blocks. This tutorial will give an overview about high quality memory testing in industrial environment, and how Semiconductor Companies are surviving in competitive markets by delivering high quality products and targeting for Zero Defect escapes for specific customers (e.g., Automotive, Medical Systems, Avionics, etc.). Also, an overview about closing the loop with memory designers and process engineers in early phase of the design is highlighted. Such loop could easily improve the test & yield of embedded memories in short market time window by taking decisive actions on layout level.","PeriodicalId":320365,"journal":{"name":"2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)","volume":"843 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SRAM cell current in low leakage design SRAM电池电流低漏设计

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.28

D. Kwai, Ching-Hua Hsiao, C. Kuo, C. Chuang, M. Hsu, Yi-Chun Chen, Yu-Ling Sung, H. Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou

{"title":"SRAM cell current in low leakage design","authors":"D. Kwai, Ching-Hua Hsiao, C. Kuo, C. Chuang, M. Hsu, Yi-Chun Chen, Yu-Ling Sung, H. Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou","doi":"10.1109/MTDT.2006.28","DOIUrl":"https://doi.org/10.1109/MTDT.2006.28","url":null,"abstract":"This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mum 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access","PeriodicalId":320365,"journal":{"name":"2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131095941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SRAM Design Techniques for Sub-nano CMOS Technology 亚纳米CMOS技术的SRAM设计技术

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.29

Jordan Lai

{"title":"SRAM Design Techniques for Sub-nano CMOS Technology","authors":"Jordan Lai","doi":"10.1109/MTDT.2006.29","DOIUrl":"https://doi.org/10.1109/MTDT.2006.29","url":null,"abstract":"The scaling of CMOS technology has significant impacts on SRAM cell – random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve. Besides that, the large leakage current caused by the low threshold voltage and thin gate oxide let the sub-nano SRAM design have huge static power. This makes portable electronics applications become difficult. In this talk, several design techniques used to minimize the static power consumption will be addressed and compared first. Second, in order to increase the read/write margins of SRAM cell, the VDC (Voltage Down Converter) approach will be discussed. It is founded that by using a simple VDC design, the RM (Read Margin) and WM (Write Margin) can be significantly improved and let the SRAM design be functional in the 0.7V range. The yield of the SRAM chip can also be dramatically improved. Incorporated with a resistor-less BGR (Bandgap Reference) design, this VDC can be used for static power reduction, read margin and write margin improvement, programmable voltage and voltage clamping.","PeriodicalId":320365,"journal":{"name":"2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114271501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory P+-和N+- poly SONOS NAND闪存的程序、擦除和数据保留特性的详细比较

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.10

V. C. Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, L. Kuo, Shi-Hsien Chen, Houng-Chi Wei, H. Hwang, S. Pittikoun

引用次数: 3

On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components 软、中栅极氧化物击穿和工艺变异性对SRAM元件参数值的综合影响

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.23

Hua Wang, M. Corbalan, F. Catthoor, W. Dehaene

{"title":"On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components","authors":"Hua Wang, M. Corbalan, F. Catthoor, W. Dehaene","doi":"10.1109/MTDT.2006.23","DOIUrl":"https://doi.org/10.1109/MTDT.2006.23","url":null,"abstract":"The effect of gate oxide breakdown has long been studied in the context of device functional failure in the past. As technology node scales down to very deep submicron (VDSM) era, such an effect starts to influence the performance and power consumption of digital circuits within their lifetime. Meanwhile, process variability like threshold voltage shift due to e.g., device dopant fluctuation and/or line edge roughness effects also leads to significant shift of the parametric figures for performance and energy of these circuits at sub 100nm era. Further scaling will definitely lead to the co-existence of both effects in a single circuit. In this paper, we present the experimental analysis on the impact combining gate oxide breakdown and process variability on the energy and delay figures of SRAM cell and sense amplifier. Hspice simulations at 65nm technology node indicate a significantly larger shift in both energy and delay of these components than in the cases with either single effect when using the thinner oxide found in 45/32 nm technologies. The actual behavior of the circuits under such a situation becomes more difficult to predict and control, thus bringing a huge challenge to a successful design in the VDSM era","PeriodicalId":320365,"journal":{"name":"2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127808402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Roadmap of the Flash Memory Flash Memory路线图

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.27

R. Shirota

引用次数: 0