2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)最新文献

Future Prospective of Programmable Logic Non-volatile Device 可编程逻辑非易失性器件的未来展望

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.16

C. Hsu

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引用次数: 4

New on-Chip DFT and ATE Features for Efficient Embedded Memory Test 新的片上DFT和ATE功能用于高效嵌入式存储器测试

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.20

P. Muhmenthaler

{"title":"New on-Chip DFT and ATE Features for Efficient Embedded Memory Test","authors":"P. Muhmenthaler","doi":"10.1109/MTDT.2006.20","DOIUrl":"https://doi.org/10.1109/MTDT.2006.20","url":null,"abstract":"Testing of embedded memories, independent whether it is of volatile or non-volatile type, is based on various kinds of built-in self-test. This test solution is often driven by the fact that the system application does not provide an atspeed signal interface at the product pins. In complex SoC designs it is furthermore mandatory to do BIST as there are multiple memories of various size and organization integrated onto one chip. Given the fact that multi-site testing is state of the art even for highly complex SoCs the requirements onto the available test equipment (ATE) depend on the selection whether the product is dominated by memory or by logic/mixed signal or RF functions. This often leads to less efficient test solutions and requires multi insertion test flows in production. Here a new approach will be presented to bridge this challenging scenario. It contains a new type of signal and information handling interface between the device under test and the tester. The revolutionary change is that the ATE will act in a slave mode during a significant fraction of the manufacturing test while the DUT controls timing as well as data flow. Such new interface can serve the needs for data collection with focus on diagnosis (scan test diagnosis) at volume manufacturing as well as the complex handling of fail bit data at zero test time overhead. The basic building blocks either on-chip or in the ATE instrumentation will be explained. Especially in testing multiple embedded memories on multiple chips at the same time the throughput increase will be extraordinary.","PeriodicalId":320365,"journal":{"name":"2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128637894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment 基于顶层金属分配的不同通孔层可编程的FlexiVia ROM编译器

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.14

D. Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, M. Hsu, Yu-Zhen Liao, S. Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu

引用次数: 0

A March-based algorithm for location and full diagnosis of all unlinked static faults 一种基于march的非链接静态故障定位和全面诊断算法

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.5

T. A. Gyonjyan, Gurgen Harutunyan, V. Vardanian

引用次数: 1

DRAM Industry Trend DRAM产业趋势

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.11

P. Pai

引用次数: 0

Novel memory organization and circuit designs for efficient data access in applications of 3D graphics and multimedia coding 三维图形和多媒体编码应用中有效数据访问的新颖存储组织和电路设计

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.22

Shen-Fu Hsiao, Yonghao Chen, Ming-Yu Tsai, Tze-Chong Cheng

引用次数: 1

DDR2 DRAM output timing optimization DDR2 DRAM输出时序优化

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.9

J. Vollrath, J. Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson

引用次数: 4

MRAM write error categorization with QCKBD 用QCKBD对MRAM写错误进行分类

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.19

Y. Shimizu, H. Aikawa, K. Hosotani, N. Shimomura, T. Kai, Y. Ueda, Y. Asao, Y. Iwata, K. Tsuchida, S. Ikegawa

引用次数: 3

A new 1T DRAM cell with enhanced floating body effect 一种新型1T DRAM电池，具有增强的浮体效应

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.6

Jyi-Tsong Lin, M. Chang

引用次数: 8

Improved representatives for unrepairability judging and economic repair solutions of memories 改进了记忆的不可修复性判断和经济修复方案

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) Pub Date : 2006-08-02 DOI: 10.1109/MTDT.2006.18

Hsing-Chung Liang, LeeAnn Tzeng

引用次数: 0