DDR2 DRAM output timing optimization

Abstract

The speed of DRAMs is increasing from generation to generation. This paper gives an overview of typical DRAM output timing challenges. Tight output timing specifications in the order of several 100ps are presented. Specification requirements lead to efforts to improve the output driver design. A systematic test strategy evaluates limits of automatic test equipment (ATE) overall timing accuracy (OTA) and device performance. Systematic output timing characterization data leads to guidelines for design improvements. A good characterization strategy gives a feedback to the design of specific weaknesses of output drivers and enables ATEs to test these parameters with high accuracy