New on-Chip DFT and ATE Features for Efficient Embedded Memory Test

Abstract

Testing of embedded memories, independent whether it is of volatile or non-volatile type, is based on various kinds of built-in self-test. This test solution is often driven by the fact that the system application does not provide an atspeed signal interface at the product pins. In complex SoC designs it is furthermore mandatory to do BIST as there are multiple memories of various size and organization integrated onto one chip. Given the fact that multi-site testing is state of the art even for highly complex SoCs the requirements onto the available test equipment (ATE) depend on the selection whether the product is dominated by memory or by logic/mixed signal or RF functions. This often leads to less efficient test solutions and requires multi insertion test flows in production. Here a new approach will be presented to bridge this challenging scenario. It contains a new type of signal and information handling interface between the device under test and the tester. The revolutionary change is that the ATE will act in a slave mode during a significant fraction of the manufacturing test while the DUT controls timing as well as data flow. Such new interface can serve the needs for data collection with focus on diagnosis (scan test diagnosis) at volume manufacturing as well as the complex handling of fail bit data at zero test time overhead. The basic building blocks either on-chip or in the ATE instrumentation will be explained. Especially in testing multiple embedded memories on multiple chips at the same time the throughput increase will be extraordinary.